Method and apparatus for optimization of amplifier with adjustable output range

• US 7,009,454 B2
• Filed: 01/20/2004
• Issued: 03/07/2006
• Est. Priority Date: 01/20/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Anadigics Incorporated (Coherent Corp.)
• Inventors: Rategh, Hamid Reza, Soltan, Mehdi Frederik
• Primary Examiner(s): Jeanglaude, Jean
• Assistant Examiner(s): Nguyen, John B
• Application Number:
  US10/760,698
• Publication Number:
  US 20050156670A1
• Time in Patent Office: 777 Days
• Field of Search: 330/295, 330/277, 330/302, 330/124.R, 330/306, 330/296, 330/286, 330/303, 330/285, 330/297
• US Class Current: 330/295
• CPC Class Codes: H03F 1/483 with field-effect transistors

Abstract

A method and apparatus for an amplifier, such as a radio frequency amplifier embodied as an integrated circuit is disclosed. Embodiments provide for a wide range of operating powers with good energy efficiency at many power levels. Resonant components act to provide consistent operating parameters over the wide range of power levels used. The invention may operate in the microwave region or at other RFs.

Claims

1. A method for amplifying comprising:

operating a first amplifier comprising a first active device supplying a first signal to a first matching network, the first matching network producing a first output, the first matching network including a first set of devices having a first resonance at a normal operating frequency of the circuit; and

operating a second amplifier comprising a second active device supplying a second signal to a second matching network, the second matching network producing a second output, the second matching network including a second set of devices having a second resonance at the normal operating frequency of the circuit;

wherein the respective outputs of the first and second amplifiers are summed at a summing node to produce a summed signal and,

wherein a circuit output signal is derived from the summed signal and,

wherein the method has at least a first operating mode and a second operating mode and,

wherein whenever the method is in the first operating mode;

the first and second active devices are biased to be active and turned on and,

wherein whenever the method is in the second operating mode;

the second active device is biased into at least a partially cutoff condition and the second matching network presents high impedance at the summing node, the high impedance being caused by the second resonance at the normal operating frequency;

wherein the first matching network is a high-pass “

π

”

match structure;

whereby the circuit operates with high efficiency and higher power in the first operating mode and the circuit operates with high efficiency and lower power in the second operating mode.

2. A circuit for amplifying comprising:

a first amplifier comprising a first active device supplying a first signal to a first matching network, the first matching network producing a first output, the first matching network including a first set of devices having a first resonance at a normal operating frequency of the circuit; and

a second amplifier comprising a second active device supplying a second signal to a second matching network, the second matching network producing a second output, the second matching network including a second set of devices having a second resonance at the normal operating frequency of the circuit;

wherein the respective outputs of the first and second amplifiers are summed at a summing node to produce a summed signal and,

wherein a circuit output signal is derived from the summed signal and,

wherein the circuit has at least a first operating mode and a second operating mode and,

wherein whenever the circuit is in the first operating mode;

the first and second active devices are biased to be active and turned on and,

wherein whenever the circuit is in the second operating mode;

the second active device is biased into at least a partially cutoff condition and the second matching network presents high impedance at the summing node, the high impedance being caused by the second resonance at the normal operating frequency;

wherein the first matching network is a high-pass “

π

”

match structure

whereby the circuit operates with high efficiency and higher power in the first operating mode and the circuit operates with high efficiency and lower power in the second operating mode.