Comprehensive erase verification for non-volatile memory

• US 7,009,889 B2
• Filed: 05/28/2004
• Issued: 03/07/2006
• Est. Priority Date: 05/28/2004
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Wan, Jun, Lutze, Jeffrey W., Chen, Jian, Tran, Dat, Ponnuru, Kiran
• Primary Examiner(s): Phung, Anh
• Assistant Examiner(s): NGUYEN, DANG T
• Application Number:
  US10/857,245
• Publication Number:
  US 20050265081A1
• Time in Patent Office: 648 Days
• Field of Search: 365/185.29, 365/185.17, 365/185.21, 365/185.33, 365/189.05, 365/149, 365/189.06
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

Claims

1. A method of erasing non-volatile memory, comprising:

erasing a group of non-volatile storage elements during user operation;

performing an erase verification operation to determine if said group of non-volatile storage elements is erased, said performing determines whether there is a first current flow above a first minimum current level in a first direction through said group;

reading said group of non-volatile storage elements for an erased state, said reading determines whether there is a second current flow above a second minimum current level in a second direction through said group; and

verifying that said group is erased if said erase verification operation determines that said group is erased and said step of reading reads said group as erased.

2. A method according to claim 1, wherein:

said step of reading includes simultaneously reading each storage element of said group for an erased state.

3. A method according to claim 2, wherein simultaneously reading each storage element of said plurality comprises:

applying a first voltage to a control gate of each storage element of said group; and

determining whether said second current flow through said group with said first voltage applied is above said second minimum current level.

4. A method according to claim 3, wherein:

said step of reading reads said group as erased if said second current flow is above said first second minimum current level.

5. A method according to claim 1, wherein:

said first minimum current level and said second minimum current level are equal.

6. The method of claim 1, wherein:

said step of performing an erase verification operation determines whether there is a first current flow above a first minimum current level by determining whether a charge at a portion of said group is above a minimum voltage level.

7. A method according to claim 1, wherein:

said reading determines whether said second current flow through said group is above said second minimum current level by determining whether a charge at a portion of said group is below a minimum voltage level.

8. A method according to claim 1, further comprising:

marking said group as defective if said step of performing an erase verification operation determines that said group is erased and said step of reading does not read said at last one storage element as erased.

9. A method according to claim 1, wherein:

said step of performing an erase verification operation includes applying a first set of bias conditions to said group; and

said step of reading includes applying a second set of bias conditions to said group.

10. A method according to claim 9, wherein:

said step of performing an erase verification operation includes determining whether a charge at a first portion of said group is above a minimum level when said first set of bias conditions is applied; and

said step of reading includes determining whether a charge at a second portion of said group is below a maximum level when said second set of bias conditions is applied.

11. A method according to claim 9, wherein:

said step of performing an erase verification operation determines that said group is erased if said charge at said first portion is above said minimum level; and

said step of reading reads said at least one storage element as erased if said charge at said second portion is below said maximum level.

12. A method according to claim 9, wherein:

said step of determining whether a charge at a first portion of said group is above a minimum level determines whether said charge is above said minimum level after a period of time after applying said first set of bias conditions; and

said step of determining whether a charge at a second portion of said group is below a maximum level determines whether said charge is below said maximum level after a period of time after applying said second set of bias conditions.

13. A method according to claim 9, wherein:

said first portion and said second portion are a same portion.

14. A method according to claim 13, wherein:

said group is a NAND string;

said NAND string includes a source side and a drain side, said drain side is coupled to a bit line; and

said same portion is said drain side.

15. A method according to claim 14, wherein:

said NAND string includes a select gate;

said step of applying said first set of bias conditions causes a current flow from said source side to said drain side when said string is erased; and

said step of applying said second set of bias conditions causes a current flow from said drain side to said source side when said string is erased and said select gate is not defective.

16. The method of claim 15, wherein:

said select gate is coupled to said drain side of said string.

17. The method of claim 15, wherein:

said select gate is coupled to said source side of said string.

18. A method according to claim 9, wherein said step of applying a first set of bias conditions includes:

applying a first voltage to each storage element of said group, said first voltage is sufficient to turn on an erased storage element;

applying a second voltage at a source side of said group; and

applying a third voltage at a drain side of said group, said third voltage is less than said second voltage.

19. A method according to claim 9, wherein said step of applying a second set of bias conditions includes:

applying a first voltage to each storage element of said group, said first voltage is sufficient to turn on an erased storage element;

applying a second voltage at a source side of said group; and

applying a third voltage at a drain side of said group, said third voltage is greater than said second voltage.

20. A method according to claim 19, wherein:

said first voltage is not sufficient to turn on a programmed storage element.

21. A method according to claim 1, wherein:

said group is part of a block of storage elements; and

said method further comprises marking said block as defective if said step of performing an erase verification operation determines that said group is erased and said step of reading does not read said at least one storage element as erased.

22. A method according to claim 1, wherein:

said group of non-volatile storage elements are binary storage elements.

23. A method according to claim 1, wherein:

said group of non-volatile storage elements are multi-state storage elements.

24. A method according to claim 1, wherein:

said group of non-volatile storage elements are flash storage elements.

25. A method according to claim 1, wherein:

said group of storage elements is part of an array of storage elements;

said array of storage elements is in communication with a host system; and

said array of storage elements is removable from said host system.

26. A method according to claim 1, further comprising:

enabling a program operation of said group if said step of performing an erase verification operation determines that said group is erased and said step of reading reads said at least one storage element as erased.

27. A method according to claim 8, wherein:

said step of marking said group as defective includes mapping said group to another group of non-volatile storage elements.

28. A method according to claim 2, wherein:

said step of simultaneously reading each storage element comprises performing a NAND string read operation.

29. A method according to claim 1, wherein:

said group of non-volatile storage elements are part of a memory system;

said steps of performing an erase verification operation and reading said group are performed by a controller; and

said controller is part of said memory system.

30. A memory system, comprising:

a group of non-volatile storage elements located in a host system, said group includes a source side and a drain side; and

a managing circuit in communication with said group, said managing circuit causes an erase operation to be performed for said group, said managing circuit performs an erase verification operation to determine whether said group is erased and reads at least one non-volatile storage element of said group for an erased state after erasing said group, said managing circuit reads said at least one non-volatile storage element for an erased state by applying a first voltage sufficient to turn on an erased storage element to each non-volatile storage element of said group, applying a second voltage at said source side, and applying a third voltage at said drain side, said third voltage is greater than said second voltage, wherein said managing circuit verifies that said group is erased when said erase verification operation determines that said group is erased and said at least one non-volatile storage element is read as erased.

31. A memory system according to claim 30, wherein:

said group of non-volatile storage elements are connected in series.

32. A memory system according to claim 30, wherein:

said group is a NAND string.

33. A memory system according to claim 30, wherein:

said managing circuit simultaneously reads each storage element of said group for an erased state, wherein said managing circuit applies said first voltage to each storage element of said group and determines whether a current flow through said group with said first voltage applied is above a minimum current level to simultaneously read each storage element.

34. A memory system according to claim 30, wherein:

said group of non-volatile storage elements are multi-state NAND flash memory devices.

35. A memory system according to claim 30, wherein:

said memory system further comprises an array of storage elements;

said group is part of said array; and

said array is removable from said host system.

36. A memory system according to claim 30, wherein:

said managing circuit includes at least one of a controller and a state machine.

37. A memory system according to claim 30, wherein:

said managing circuit performs said erase verification operation and reads at least one storage element during user operation of said memory system.

38. A method of operating non-volatile memory, comprising:

performing a plurality of programming operations to store user data in a memory system; and

performing a plurality of erase operations to erase said user data, wherein at least one of said erase operations includes the steps of;

erasing a group of non-volatile storage elements of said memory system;

performing an erase verification operation to determine whether said group is erased after said step of erasing, said performing includes determining whether a charge at a first portion of said group is above a minimum level,

reading at least one non-volatile storage element of said group for an erased state, said reading includes determining whether a charge at a second portion of said group is below a maximum level, and

verifying that said group is erased if said step of performing an erase verification operation determines that said group is erased and said step of reading reads said at last one storage element as erased.

39. A method according to claim 38, wherein:

said step of reading includes reading said group for an erased state, wherein reading said group includes simultaneously reading each storage element of said group by applying a set of bias conditions to said group and testing conduction in a first direction through said group.

40. A method according to claim 39, wherein:

said step of performing an erase verification operation tests conduction in a second direction through said group.

41. A method according to claim 38, wherein:

said group of non-volatile storage elements are multi-state flash storage elements.

42. A method according to claim 38, wherein:

said group is part of an array of storage elements;

said array is in communication with a host system; and

said array is removable from said host system.

43. A method according to claim 38, wherein:

said group of non-volatile storage elements are part of a memory system;

said step of performing a plurality of erase operations is performed by a controller; and

said controller is part of said memory system.

44. A method of erasing non-volatile memory, comprising:

erasing a group of non-volatile storage elements during user operation;

performing an erase verification operation to determine if said group of non-volatile storage elements is erased;

reading said group of non-volatile storage elements for an erased state, said reading includes applying a first voltage sufficient to turn on an erased storage element to each non-volatile storage element of said group, applying a second voltage at a source side of said group, and applying a third voltage at a drain side of said group, said third voltage is greater than said second voltage; and

verifying that said group is erased if said erase verification operation determines that said group is erased and said step of reading reads said group as erased.

45. A method according to claim 44, wherein:

said performing an erase verification operation determines whether there is a first current flow above a first minimum current level in a first direction through said group.

46. A method according to claim 45, wherein:

said reading said group determines whether there is a second current flow above a second minimum current level in a second direction through said group.

47. A method according to claim 46, wherein:

said performing an erase verification operation determines whether there is a first current flow above a first minimum current level by determining whether a charge at a first portion of said group is above a minimum voltage level; and

said reading said group determines whether there is a second current flow above a second minimum current level by determining whether a charge at a second portion of said group is below a maximum voltage level.

48. A method according to claim 47, wherein:

said first portion and said second portion are a same portion; and

said minimum voltage level and said maximum voltage level are equal.

49. A method according to claim 44, wherein:

said performing an erase verification operation includes applying a first set of bias conditions to said group; and

said reading said group includes applying a second set of bias conditions to said group.

50. A non-volatile memory system, comprising:

a group of non-volatile storage elements located in a host system; and

a managing circuit in communication with said group, said managing circuit causes an erase operation to be performed for said group, said managing circuit performs an erase verification operation to determine whether said group is erased and reads at least one non-volatile storage element of said group for an erased state after erasing said group, said managing circuit reads said at least one non-volatile storage element by testing conduction in a first direction through said group and performs said erase verification operation by testing conduction in a second direction through said group, said managing circuit verifies that said group is erased when said erase verification operation determines that said group is erased and said at least one non-volatile storage element is read as erased.

51. A method according to claim 50, wherein:

testing conduction in a first direction includes determining whether a charge at a first portion of said group is below a maximum level while applying a first set of bias conditions to said group; and

testing conduction in a second direction includes determining whether a charge at a second portion of said group is above a minimum level while applying a second set of bias conditions to said group.

52. A method according to claim 51, wherein:

said first portion and said second portion are a same portion.

53. A method according to claim 51, wherein applying said first set of bias conditions includes:

applying a first voltage to each storage element of said group, said first voltage is sufficient to turn on an erased storage element;

applying a second voltage at a source side of said group; and

applying a third voltage at a drain side of said group, said third voltage is greater than said second voltage.

54. A method according to claim 51, wherein applying said second set of bias conditions includes:

applying a first voltage to each storage element of said group, said first voltage is sufficient to turn on an erased storage element;

applying a second voltage at a source side of said group; and

applying a third voltage at a drain side of said group, said third voltage is less than said second voltage.

55. A method of operating non-volatile memory, comprising:

performing a plurality of programming operations to store user data in a memory system; and

performing a plurality of erase operations to erase said user data, wherein at least one of said erase operations includes the steps of;

erasing a group of non-volatile storage elements of said memory system;

performing an erase verification operation to determine whether said group is erased after said step of erasing, said erase verification operation tests conduction in a first direction through said group,

reading at least one non-volatile storage element of said group for an erased state, said reading tests conduction in a second direction through said group, and

verifying that said group is erased if said step of performing an erase verification operation determines that said group is erased and said step of reading reads said at last one storage element as erased.

56. A method according to claim 55, wherein:

testing conduction in a first direction includes determining whether a first current flow through said group is above a first minimum current level while applying a first set of bias conditions; and

testing conduction in a second direction includes determining whether a second current flow through said group is above a second minimum current level while applying a second set of bias conditions to said group.

57. A method according to claim 56, wherein:

said first minimum current level and said second minimum current level are equal.

58. A method according to claim 56, wherein applying said first set of bias conditions includes:

applying a first voltage to each storage element of said group, said first voltage is sufficient to turn on an erased storage element;

applying a second voltage at a source side of said group; and

applying a third voltage at a drain side of said group, said third voltage is less than said second voltage.

59. A method according to claim 56, wherein applying said second set of bias conditions includes:

applying a first voltage to each storage element of said group, said first voltage is sufficient to turn on an erased storage element;

applying a second voltage at a source side of said group; and

applying a third voltage at a drain side of said group, said third voltage is greater than said second voltage.