CMOS process silicon waveguides

• US 7,010,208 B1
• Filed: 06/24/2003
• Issued: 03/07/2006
• Est. Priority Date: 06/24/2002
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Luxtera Incorporated (Cisco Systems, Inc.)
• Inventors: Gunn, Lawrence C. III, Capellini, Giovanni, Rattier, Maxime Jean, Pinguet, Thierry J.
• Primary Examiner(s): Font, Frank G.
• Assistant Examiner(s): Kalivoda, Christopher M.
• Application Number:
  US10/606,297
• Time in Patent Office: 987 Days
• Field of Search: None
• US Class Current: 385/131
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/132 by deposition of thin films

Abstract

A standard CMOS process is used to fabricate optical and electronic devices at the same time on a monolithic integrated circuit. In the process, a layer of metallic salicide can be depsoited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into the core of an optical waveguide will damage the waveguide and prevent the passage of light through that section of the waveguide. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.

Claims

1. An optical waveguide on a substrate, where the optical waveguide is comprised of:

a core comprised of monocrystalline silicon, where the core and a silicon body of a transistor are formed from the same layer of monocrystalline silicon on the same substrate, and

a cladding comprised of a plurality of dielectric materials, where at least one of the plurality of dielectric materials is comprised of a salicide block layer used during the fabrication of a transistor on the same substrate.

2. The optical waveguide of claim 1, wherein the substrate is comprised of a layer of silicon dioxide disposed on a second lower layer of monocrystalline silicon.

3. The optical waveguide of claim 2, wherein the cladding includes a bottom layer comprised of the layer of silicon dioxide, where the silicon dioxide layer is used to electrically isolate the transistor formed on the substrate from the lower layer of monocrystalline silicon.

4. The optical waveguide of claim 1, wherein the substrate is comprised of:

a first layer comprised of monocrystalline silicon,

a second layer comprised of silicon dioxide disposed on the first layer,

a third layer comprised of monocrystalline silicon disposed on the second layer and

a fourth layer comprised of silicon dioxide disposed on the third layer.

5. The optical waveguide of claim 4, wherein the cladding includes a bottom layer comprised of the fourth layer of the substrate, where the fourth layer is used to electrically isolate the transistor formed on the substrate from the third layer.

6. The optical waveguide of claim 1, wherein the substrate is comprised of sapphire.

7. The optical waveguide of claim 1, wherein the substrate is comprised of a plurality of layers of silicon on nothing, where the waveguide core is formed from the top layer of silicon.

8. The optical waveguide of claim 1, wherein the cladding includes a bottom cladding comprised of a top layer of the substrate.

9. The optical waveguide of claim 1, wherein the cladding includes a layer of dielectric material formed at the same time as a sidewall passivation for the silicon body of a transistor.

10. The optical waveguide of claim 1, wherein the cladding includes a plurality of layers of dielectric material formed at the same time as a plurality of dielectric materials used as a gate spacer for a transistor.

11. The optical waveguide of claim 1, wherein the cladding includes a layer of dielectric material formed at the same time as a contact punch-through layer for a transistor.

12. The optical waveguide of claim 1, wherein the cladding includes a layer of dielectric material formed at the same time as an inter-level dielectric for a transistor.

13. The optical waveguide of claims 9, 10 or 11 wherein the layer of dielectric material included in the cladding is selected from the group comprising:

silicon dioxide and silicon nitride.

14. The optical waveguide of claim 1, wherein at least one of the plurality of dielectric materials is selected from a group of dielectrics used at the same time to form a dielectric element of a transistor, the group of dielectrics comprising:

a contact punch-through layer, an inter-layer dielectric film, a gate spacer, a salicide block, a dielectric spacer, a sidewall passivation film, an isolation dielectric, an oxide spacer and a field oxide.

15. The optical waveguide of claim 14, wherein thermal oxidation is used to form a sidewall passivation film, where the sidewall passivation film is used as one of a plurality of dielectric materials for the optical waveguide and is formed at the same time as the passivation film for the body of a transistor.

16. The optical waveguide of claim 1, wherein at least one of the plurality of dielectric materials is selected from the group comprising:

SiO₂, SiCOH, SiCOF, Si₃N₄, SiON, BPSG and silicon-based materials including one or more of the following elements;

oxygen, carbon, nitrogen, hydrogen, boron, phosphorus, fluorine and arsenic.

17. The optical waveguide of claim 1, wherein the transistor is selected from the group comprising:

a CMOS transistor, a BiCMOS transistor, a bipolar junction transistor (BJT) and a junction FET (JFET) transistor.

18. The optical waveguide of claim 1, wherein the salicide block layer is used as a gate spacer during the fabrication of a transistor on the same substrate.