Dynamic creation and modification of wafer test maps during wafer testing

• US 7,010,451 B2
• Filed: 04/17/2003
• Issued: 03/07/2006
• Est. Priority Date: 04/17/2003
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Velichko, Sergey A., Dorough, Michael J., Gravelle, Robert M.
• Primary Examiner(s): Tsui, Carol S. W.
• Assistant Examiner(s): KIM, PAUL L
• Application Number:
  US10/417,640
• Publication Number:
  US 20040210413A1
• Time in Patent Office: 1,055 Days
• Field of Search: 324/765, 324/754, 324/769, 324/158.1, 438/5, 438/10, 438/14, 438/17, 716/1, 716/4, 382/145, 702/117, 702/118
• US Class Current: 702/117
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875

Abstract

Methods, systems, and apparatuses provide dynamic creation and modification of wafer test maps. Test plans are defined for a testing session of a wafer lot. The test plan is associated with a number of seed map patterns. During a wafer lot testing session, test results are dynamically obtained and examined at run-time of a test. Moreover, the seed map patterns are overlaid on the test sites defined in the test plan. If the test result statistics are outside of defined threshold tolerance levels, then a new wafer test map is created or modified at run-time, according to corresponding seed map patterns. If seed map patterns are within the intersection of valid test sites, then seed map patterns are created at run-time.

Claims

1. A method for dynamic wafer map creation, comprising:

testing a wafer using a first test map;

acquiring one or more candidate patterns during testing;

identifying a subset of test locations within the wafer that intersect with one or more of the candidate patterns; and

dynamically creating one or more second test maps based on the one or more patterns and the subset of intersecting test locations for use during a same testing session.

2. The method of claim 1 further comprising, using one or more results associated with testing the wafer with the first test map when creating the one or more second test maps.

3. The method of claim 1 further comprising, dynamically performing tests on the wafer for a number of the one or more second test maps.

4. The method of claim 3 wherein in dynamically performing, a number of the one or more second test maps are queued for subsequent testing.

5. The method of claim 3 further comprising, forming a composite test map from the one or more second test maps.

6. The method of claim 1 wherein in detecting, the one or more patterns include test locations for the wafer that intersect predefined geometric patterns.

7. A method for dynamic wafer map creation, comprising:

loading a wafer test plan;

testing a first test map against a wafer;

obtaining first results;

determining patterns for additional testing on the wafer by locating a number of test sites defined in the test plan tat intersect a number of predefined seeded patterns associated with one or more second test maps; and

creating dynamic instances of the one or more second test maps for testing during a same testing session as the first test map by using the located test sites and the first results.

8. The method of claim 7 wherein in obtaining a number of the first results include results obtained from sensors indicating that values associated with the test measurements and results exceed predefined thresholds.

9. The method of claim 7 wherein in creating, the instances of the one or more second test maps include specific tests to be performed on a number of the located test sites of the wafer.

10. The method of claim 7 wherein in testing, the testing is suspended from the first test map based on predefined values dynamically being obtained from the first results, and testing is dynamically switched to one or more of the second test maps.

11. The method of claim 7 further comprising, combining the one or more second test maps into a composite test map.

12. The method of claim 11 further comprising, dynamically testing the wafer using the composite test map.

13. The method of claim 7 further comprising, concurrently testing at least two of the one or more second test maps against the wafer in parallel.

14. The method of claim 7 wherein in creating, a number of the one or more second test maps are selected from a data store of test map templates.

15. A method for dynamic wafer map creation, comprising:

executing a first test on a wafer using a first test map;

identifying test sites on the wafer available for testing;

matching a number of the test sites with patterns associated with one or more second test maps; and

dynamically executing one or more second tests on the wafer using the one or more second test maps, in response to matching and during a same testing session as the first test.

16. The method of claim 15 wherein in executing, the test sites of the one or more second test maps are tested in a serpentine prober movement pattern.

17. The method of claim 15 wherein in executing, the test sites of the one or more second test maps are tested in a non-serpentine prober movement pattern.

18. The method of claim 15 further comprising, using results associated with the first test with the matching patterns to select the one or more second test maps.

19. A dynamic wafer testing system, comprising:

a lot of wafers subject to a testing session associated with a test plan;

a first test map associated with the test plan;

a number of test sites associated with each of the wafers in the lot and identified in the test plan; and

a test station controller that initiates testing of the first test map on a first wafer in the lot, and that acquires the test sites identified in the test plan, and wherein the test station controller dynamically identifies a number of additional test maps associated with patterns of the test sites on the first wafer, and dynamically tests the first wafer and the remaining wafers using the additional test maps identified during the same testing session.

20. The dynamic wafer testing system of claim 19, wherein the first test map is dynamically created after analyzing the test plan and comparing a number of test sites in the test plan to a default seed pattern.

21. The dynamic wafer testing system of claim 20, wherein the default seed pattern identifies a percentage of the test sites that are needed on the first wafer and matched to the default seed pattern in order to create the first test map.

22. The dynamic wafer testing system of claim 20, wherein the default seed pattern identifies a checkerboard pattern of test sites that are needed on the first wafer and matched to the default seed pattern in order to create the first test map.

23. The dynamic wafer testing system of claim 19, wherein the patterns are stored and acquired from a data store during the testing session.

24. The dynamic wafer testing system of claim 19, wherein the patterns are dynamically altered based on results of testing the first wafer of the lot.

25. The dynamic wafer testing system of claim 19, wherein while the first wafer in the lot is being tested a next wafer in the lot begins testing in parallel during the testing session.

26. The dynamic wafer testing system of claim 19, wherein testing on the first wafer using the first test map completes before the additional test maps are created and tested against the first wafer and the remaining wafers in the lot.

27. A dynamic wafer testing system, comprising:

a wafer that is subject to testing;

a processor instance;

a sensor instance associated with each test register included within the processor instance; and

wherein during testing of the wafer one of the sensor instances detects a measurement statistic that exceeds a predefined threshold, and based on that event a new wafer test map is dynamically identified and used to continue testing the wafer during a same test session.

28. The dynamic wafer testing system of claim 27, wherein a new wafer test map identifies sites on the wafer for testing and types of testing to be performed on the sites of the wafer.

29. The dynamic wafer testing system of claim 27, wherein the new wafer test map preempts the testing of a previous test map that is processing on the processor instance when the measurement statistic exceeds the predefined threshold.

30. The dynamic wafer testing system of claim 27, wherein the new wafer test map is created by identifying a desired geometric pattern associated with the new wafer test that intersects a desired number of testing sites on the wafer, and wherein the testing sites are identified in a testing plan.

31. A wafer subject to dynamic testing from instructions accessible to a computer-readable medium, where the instructions comprise:

identifying a test plan associated with testing the wafer;

identifying test sites on the wafer from the test plan;

initiating a first test map created from the test plan to begin testing of the wafer; and

dynamically creating one or more second test maps for continued testing of the wafer during a same testing session.

32. The wafer of claim 31 wherein in dynamically creating, the one or more second test maps are identified by dynamic measurement values obtained during testing of the wafer using the first test map.

33. The wafer of claim 31 wherein in initiating the first test map, the first test map is created based on a detected default geometric seeded pattern that can be identified from a number of the test sites that are to be tested on the wafer.

34. The wafer of claim 31 further comprising instructions for suspending the testing of the wafer against the first test map and automatically starting testing that uses one or more of the second test maps when predefined results associated with testing the first test map are detected.

35. The wafer of claim 31 wherein in dynamically creating, a number of the one or more second test maps are identified by matching patterns associated with the test sites of the wafer against patterns included within a data store that identify a number of the one or more second test maps.