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Derating factor determination for integrated circuit logic design tools

  • US 7,010,475 B2
  • Filed: 02/05/2003
  • Issued: 03/07/2006
  • Est. Priority Date: 05/03/1999
  • Status: Expired due to Fees
First Claim
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1. A method, comprising:

  • (a) providing an integrated circuit development library characterizing several different logic device cells, the library specifying a number of different timing relationships for each of the logic device cells;

    (b) determining a number of derating values for characterizing derated performance of each of the logic device cells, each of the derating values being determined by evaluating a different one of the timing relationships for each of the logic device cell descriptions at a derating condition with a first simulator; and

    (c) calculating a number of derating factors, the derating factors each being determined from a different subset of the derated condition values, the derating factors being applicable to estimate derated performance of an integrated circuit developed from the library with a second simulator, the calculating of the number of derating factors including;

    establishing a number of best cast multiplier arrays and a number of worst case multiplier arrays; and

    screening each of the best case multiplier arrays and each of the worst case multiplier arrays.

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