Derating factor determination for integrated circuit logic design tools
First Claim
1. A method, comprising:
- (a) providing an integrated circuit development library characterizing several different logic device cells, the library specifying a number of different timing relationships for each of the logic device cells;
(b) determining a number of derating values for characterizing derated performance of each of the logic device cells, each of the derating values being determined by evaluating a different one of the timing relationships for each of the logic device cell descriptions at a derating condition with a first simulator; and
(c) calculating a number of derating factors, the derating factors each being determined from a different subset of the derated condition values, the derating factors being applicable to estimate derated performance of an integrated circuit developed from the library with a second simulator, the calculating of the number of derating factors including;
establishing a number of best cast multiplier arrays and a number of worst case multiplier arrays; and
screening each of the best case multiplier arrays and each of the worst case multiplier arrays.
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Abstract
An integrated circuit development library is provided that characterizes several different logic device cells. The library specifies a number of different timing relationships for each of the logic device cells. These timing relationships are evaluated for each of the logic device cells at a first derating condition with a first simulator to provide a first set of derated condition values. The first set of derated condition values each correspond to one of the timing relationships evaluated. A first derating factor is calculated from the first set of derated condition values for estimating derated performance of an integrated circuit with a second simulator. This integrated circuit is developed from one or more of the logic device cells of the library.
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Citations
6 Claims
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1. A method, comprising:
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(a) providing an integrated circuit development library characterizing several different logic device cells, the library specifying a number of different timing relationships for each of the logic device cells; (b) determining a number of derating values for characterizing derated performance of each of the logic device cells, each of the derating values being determined by evaluating a different one of the timing relationships for each of the logic device cell descriptions at a derating condition with a first simulator; and (c) calculating a number of derating factors, the derating factors each being determined from a different subset of the derated condition values, the derating factors being applicable to estimate derated performance of an integrated circuit developed from the library with a second simulator, the calculating of the number of derating factors including; establishing a number of best cast multiplier arrays and a number of worst case multiplier arrays; and screening each of the best case multiplier arrays and each of the worst case multiplier arrays. - View Dependent Claims (2, 3)
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4. An apparatus, comprising:
- a processing system including;
means for providing a library including a plurality of logic device cell descriptions each including a number of timing relationships; means for determining a number of derating values for characterizing derated performance of each of the logic device cells, each of the derating values being determined by evaluating a different one of the timing relationships for each of the logic device cell descriptions at a derating condition with a first simulator; and means for calculating a number of derating factors, the derating factors each being determined from a different subset of the derating values, the derating factors being applicable to estimate derated performance of an integrated circuit developed from the library with a second simulator, and wherein said calculating means includes means for establishing a number of best case multiplier arrays and a number of worst case multiplier arrays and means for screening each of the best case multiplier arrays and each of the worst case multiplier arrays. - View Dependent Claims (5, 6)
- a processing system including;
Specification