Zirconium oxide and hafnium oxide etching using halogen containing chemicals

• US 7,012,027 B2
• Filed: 01/27/2004
• Issued: 03/14/2006
• Est. Priority Date: 01/27/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Peng-Fu, Chiu, Yuan-Hung, Perng, Baw-Ching, Sung, Mei-Hui
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): PHAM, THANHHA S
• Application Number:
  US10/766,596
• Publication Number:
  US 20050164479A1
• Time in Patent Office: 777 Days
• Field of Search: 438/3, 438/199, 438/216, 438/287, 438/591, 438/594, 438710-712, 438/714, 438/717, 438/720, 438/722, 438735-738
• US Class Current: 438/710
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF₄, CHF₃, CH₂F₂, CH₃F, C₄F₈, C₄F₆, C₅F₆, BCl₃, Br₂, HF, HCl, HBr, HI, and NF₃ and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

Claims

1. A method of removing a high k dielectric layer from a substrate, comprising the steps of:

(a) providing a substrate with isolation regions and an active area between said isolation regions;

(b) depositing a high k dielectric layer on said substrate;

(c) forming a patterned gate electrode on said high k dielectric layer; and

(d) anisotropically etching through exposed portion of said high k dielectric layer with a plasma etch comprising one or more halogen containing gases;

wherein said anisotropically etching step is performed in an etch chamber and is comprised of a flow rate between about 2 and 100 standard cubic centimeters per minute (sccm) for the one or more halogen containing gases, at a temperature between 20°

C. and 200°

C.;

wherein said anisotropically etching step includes of adding one or more O₂, CO, CO₂, and N₂O as an oxidant gas having a flow rate between about 10 and 300 sccm, said oxidant gas including O₂; and

wherein said high k dielectric layer includes HfO₂, wherein said halogen containing gases includes CF₄ and CH₃F, and wherein said anisotropically etching step includes a CF₄ flow rate of about 30 sccm, a CH₃F flow rate of about 60 sccm, an O₂ flow rate of about 10 sccm, a 5 mTorr chamber pressure, a RF power of about 600 Watts and a bias power of about 200 Watts for a period of about 10 seconds.

2. The method of claim 1 further comprised of forming an interfacial layer on said substrate prior to depositing said high k dielectric layer.

3. The method of claim 2 wherein the interfacial layer is comprised of silicon oxide, silicon nitride, or silicon oxynitride with a thickness between about 1 and 30 Angstroms.

4. The method of claim 1 wherein said high k dielectric layer has a thickness from about 10 to 120 Angstroms.

5. The method of claim 1 wherein said high k dielectric layer is formed by an atomic layer deposition (ALD), chemical vapor deposition (CVD) or metal organic CVD (MOCVD) technique.

6. The method of claim 1 wherein said high k dielectric layer includes one of Ta₂O₅, TiO₂, Al₂O₃, Y₂O₃ and La₂O₅ as a minor component.

7. The method of claim 1 wherein said one or more halogen containing gases further includes least one of CHF₃, CH₂F₂, BCl₃, Br₂, HF, HCl, HBr, HI, NF₃ .

8. The method of claim 1 wherein said anisotropically etching further includes adding one or more of Ar, Xe, He, and N₂ as a inert gas having a flow rate between about 10 and 250 sccm.

9. The method of claim 1 wherein the substrate is silicon and the isolation regions are comprised of silicon oxide and the etch rate of said high k dielectric layer in step (d) is more than twice the rate of etching silicon oxide or silicon.

10. A method of removing a high k dielectric layer from a substrate, comprising the steps of:

(a) providing a substrate with isolation regions and an active area between said isolation region;

(b) depositing a high k dielectric layer on said substrate;

(c) forming a patterned gate electrode on said high k dielectric layer; and

(d) anisotropically etching through exposed portions of said high k dielectric layer with a plasma etch comprising one or more halogen containing gases;

wherein said anisotropically etching step is performed in an etch chamber and is comprised of a flow rate between about 2 and 100 standard cubic centimeters per minute (sccm) for the one or more halogen containing gases, at a temperature between 20°

C. and 200°

C. ;

wherein said anisotropically etching step includes adding one or more of Ar, Xc, He, and N₂ as a inert gas having a flow rate between about 10 and 250 sccm said inert gas includes Ar;

wherein said anisotropically etching step includes adding one or more of O₂, CO, CO₂, and N₂O, as an oxidant gas having a flow rate between about 10 and 300 sccm said oxidant gas including O₂; and

wherein said high k dielectric layer includes HfO₂ includes a CF₄ flow rate of about 5 sccm, an O₂ flow rate of about 200 sccm, an Ar flow rate of about 100 sccm with a chamber pressure of 20 mTorr, a RF power of about 600 Watts, and a bias power of about 100 Watts for a period of about 23 second to end point plus an overetch period for about an additional 23 seconds beyond end point.

11. A method comprising:

providing a substrate;

depositing a high k dielectric layer above said substrate;

forming a patterned layer above said high k dielectric layer; and

selectively etching exposed portions of said high k dielectric layer with a plasma etch comprising one or more halogen containing gases;

wherein the selectively etching step is performed in an etch chamber and is comprised of a flow rate between about 2 and 100 standard cubic centimeters per minute (sccm) for the one or more halogen containing gases, at a temperature between 20°

C. and 200°

C.;

wherein said selectively etching includes adding one or more of O₂, CO, CO₂, and N₂O as an oxidant gas having a flow rate between about 10 and 300 sccm said oxidant gas including O₂ ; and

wherein said high k dielectric layer includes HfO₂ wherein said halogen containing gases include CF₄ and CH₃F, and wherein said selectively etching includes a CF₄ flow rate of about 30 sccm a CH₃F flow rate of about 60 sccm, an O₂, flow rate of about 10 sccm, a 5 mTorr chamber pressure, a RF power of about 600 Watts and a bias power of about 200 Watts for a period of about 10 seconds.

12. The method of claim 11, including:

configuring said substrate to have isolation regions, and an active area between said isolation regions;

configuring said patterned layer to be a patterned gate electrode on said high k dielectric layer; and

carrying out said selectively etching in a manner that includes anisotropically etching through said high k dielectric layer with said plasma etch.

13. The method of claim 11, including:

configuring said patterned layer to be a patterned photoresist layer;

carrying out said selectively etching in a manner that includes anisotropically etching through said high k dielectric layer with said plasma etch;

removing said photoresist;

etch transferring said pattern in said high k dielectric layer into said substrate; and

removing said high k dielectric layer with a plasma etch comprising a halogen containing gas.

14. The method of claim 11, including:

providing an interlevel dielectric (ILD) layer over said substrate before said depositing of said high k dielectric layer;

forming in said ILD layer a pattern that includes an opening with sidewalls and a bottom;

forming a first conducting layer on the sidewalls of said opening;

thereafter carrying out said depositing of said high k dielectric layer to form said high k dielectric layer on the first conducting layer;

forming a second conducting layer on maid high k dielectric layer.