Diode and transistor design for high speed I/O

• US 7,012,304 B1
• Filed: 08/29/2000
• Issued: 03/14/2006
• Est. Priority Date: 06/30/1998
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Seshan, Krishna, Dabral, Sanjay
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): DIAZ, JOSE R
• Application Number:
  US09/651,385
• Time in Patent Office: 2,023 Days
• Field of Search: 438/203, 438/237, 438200-201, 257355-360
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

Claims

1. A method of forming an integrated circuit comprising:

forming a performance circuit occupying a first well of an integrated circuit substrate;

forming a protection circuit occupying a second well of the integrated circuit substrate separate from the first well, wherein forming the protection circuit includes;

forming a plurality of unit cells, the plurality of unit cells separated from each other to form a plurality of islands in the second well surrounded by the second well, each of the plurality of unit cells comprised of;

a block of a first doped region of a first dopant in the second well of the integrated circuit substrate occupying an area of the substrate sufficient to support a contact to the doped region, the first doped region forming an anode of a diode,

a junction region completely surrounding the first doped region, and

a contact to the doped region, wherein

the second well is doped with a first concentration of a second dopant,

forming a third doped region in the second well adjacent the junction region, the third doped region surrounding the plurality of cells and doped with a greater concentration of the second dopant, the third doped region forming a cathode of the diode; and

coupling the protection circuit to the performance circuit.

2. The method of claim 1, wherein forming a performance circuit includes forming a CMOS configuration.

3. The method of claim 2, wherein coupling the protection circuit to the performance circuit includes coupling the protection circuit to a p-channel device of the CMOS configuration.

4. The method of claim 2, wherein forming a protection circuit includes forming the diode and coupling the protection circuit to the performance circuit includes coupling the diode to a p-channel device of the CMOS configuration.

5. A method of forming an integrated circuit comprising:

forming a performance circuit occupying a first well of an integrated circuit substrate;

forming a protection circuit occupying a second well of the integrated circuit substrate separate from the first well, wherein forming the protection circuit includes;

forming a plurality of unit cells, the plurality of unit cells separated from each other to form a plurality of islands in the second well surrounded by the second well, each of the plurality of unit cells comprised of;

a block of a first doped region of a first dopant in the second well of the integrated circuit substrate occupying an area of the substrate sufficient to support a contact to the doped region,

a junction region completely surrounding the first doped region, and

a contact to the doped region, wherein the second well is doped with a first concentration of a second dopant,

forming a third doped region in the second well adjacent the junction region, the third doped region surrounding the plurality of cells and doped with a greater concentration of the second dopant; and

coupling the protection circuit to the performance circuit.

6. The method of claim 5, wherein forming a performance circuit includes forming a CMOS configuration.

7. The method of claim 6, wherein coupling the circuit to the performance circuit includes coupling the protection circuit to a p-channel device of the CMOS configuration.

8. The method of claim 6, wherein forming a protection circuit includes forming the diode and coupling the protection circuit to the performance circuit includes coupling the diode to a p-channel device of the CMOS configuration.

9. The method of claim 5, wherein the first concentration of a second dopant forms an N-type material in the second well.

10. The method of claim 5, wherein the second concentration of the second dopant forms an N⁺ material in the third doped region.