Timing recovery and phase tracking system and method

• US 7,012,983 B2
• Filed: 04/30/2001
• Issued: 03/14/2006
• Est. Priority Date: 04/28/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wakayama, Myles, Wang, Hui, Baumer, Howard A., Jiang, Xicheng, Le, Michael, Buchwald, Aaron W., Van Engelen, Jurgen, Madisetti, Avanindra
• Primary Examiner(s): Fan, Chieh M.
• Assistant Examiner(s): Perilla, Jason M.
• Application Number:
  US09/844,296
• Publication Number:
  US 20020044617A1
• Time in Patent Office: 1,779 Days
• Field of Search: 375/355, 375/354, 375/371, 375/316, 375/307, 375/356, 375/357, 375/362, 375/373, 375/376, 375/375
• US Class Current: 375/373
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0274 with Costas loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Claims

1. A system for recovering timing information from a received serial data signal, comprising:

a phase interpolator adapted to produce a data sampling signal and a phase sampling signal each having an interpolated phase responsive to a plurality of phase control signals, wherein the phase sampling signal is offset in phase relative to the data sampling signal by a predetermined amount;

a data path that samples the received serial data signal according to the data sampling signal to produce a data signal;

a phase path that samples the received serial data signal according to the phase sampling signal to produce a phase signal;

a phase detector that produces a phase error signal based on the data signal and the phase signal, wherein the phase error signal is indicative of a phase offset between the data sampling signal and the received serial data signal;

a phase error processor that produces a rotator control signal based on short-term error processing and long-term error processing of the phase error signal; and

a phase control signal rotator adapted to rotate the plurality of phase control signals and correspondingly the interpolated phases of the data sampling and the phase sampling signals in response to the rotator control signal.

2. The system of claim 1, wherein the phase error processor is adapted to cause the phase control signal rotator to rotate the plurality of phase control signals and correspondingly the interpolated phase of the data sampling signal and the phase sampling signal in a direction to reduce the phase offset between the received serial data signal and the data sampling signal.

3. The system of claim 1, wherein the rotator control signal is one of a phase-advance, a phase-retard, and a phase-hold signal, the phase control signal rotator being adapted to:

rotate the plurality of phase control signals in a first direction to advance the interpolated phase of the data sampling signal and the phase sampling signal in response to the phase-advance signal;

rotate the plurality of phase control signal in a second direction to retard the interpolated phase of the data sampling signal and the phase sampling signal in response to the phase-retard signal; and

prevent the plurality of phase control signals and correspondingly the interpolated phase of the data sampling signal and the phase sampling signal from rotating in response to the phase-hold signal.

4. The system of claim 3, wherein the phase control signal rotator includes a ring of storage elements each adapted to store one of the plurality of phase control signals, the rotator being adapted to:

concurrently shift in the first direction each of the phase control signals from a present storage element to a first adjacent storage element in response to the phase-advance signal; and

concurrently shift in the second direction each of the phase control signals from the present storage element to a second adjacent storage element in response to the phase-retard signal.

5. The system of claim 1, wherein each one of the plurality of phase control signals is a digital signal.

6. The system of claim 1, wherein the phase control signal rotator is a circular shift register including one of:

a plurality of linearly arranged storage cells each adapted to store a respective one of the plurality of phase control signals; and

a plurality of storage cells arranged in a matrix of rows and columns and linked together to form a ring structure, each of the storage cells being adapted to store a respective one of the plurality of phase control signals.

7. The system of claim 1, wherein the control signal rotator is adapted to cause the phase interpolator to rotate the interpolated phase of the data sampling signal and the phase sampling signal to one of a plurality of discrete phase values spanning a phase range of 360°

.

8. The system of claim 1, wherein the phase error processor and the phase control signal rotator are adapted to cause the phase interpolator to rotate the data sampling signal phase and the phase sampling signal phase at a rate corresponding to a frequency offset between a frequency of the data sampling signal and a frequency of the received serial data signal so as to frequency synchronize the data sampling signal to the received serial data signal.

9. The system of claim 1, wherein the phase interpolator comprises:

a plurality of reference stages adapted to control individual magnitudes of a plurality of component signals having different phases responsive to the plurality of phase control signals; and

a combining node adapted to combine the plurality of component signals into the interpolated data sampling signal.

10. The system of claim 9, wherein the plurality of component signals includes four component signals having successive phases separated at intervals of 90°

.

11. The system of claim 9, wherein the magnitude of at least one of the plurality of component signals is varied from a zero magnitude value to a maximum magnitude value in accordance with the plurality of phase control signals.

12. The system of claim 9, wherein the plurality of phase control signals is subdivided into a plurality of signal sets, each one of the plurality of signal sets being used to control the magnitude of a corresponding one of the plurality of component signals, the phase rotator including a ring of storage elements subdivided into a plurality of ring segments, each one of the plurality of ring segments being adapted to store a corresponding one of the plurality of signal sets, whereby each one of the plurality of ring segments controls the magnitude of a corresponding one of the plurality of component signals.

13. The system of claim 9, wherein the plurality of phase control signals is subdivided into a plurality of signal sets, each one of the plurality of signal sets being applied to a corresponding one of the plurality of reference stages, each one of the plurality of reference stages being adapted to control a corresponding one of the plurality of component signals in response to the corresponding one of the plurality of signal sets.

23. The system of claim 1, wherein the phase error processor comprises a short-term error processor and a long-term error processor, wherein:

the short-term error processor integrates the phase error signal over a relatively short time period to generate a phase adjust signal that responds rapidly to changes in the phase offset between the data sampling signal and the received serial data signal; and

the long-term error processor integrates the phase error signal over a relatively long time period to generate a frequency offset signal that responds slowly to changes in the phase offset between the data sampling signal and the received serial data signal.

24. The system of claim 23, wherein the short-term error processor comprises a first accumulator and the long-term error processor comprises a second accumulator.

25. The system of claim 23, wherein the phase error processor includes a rotate command generator that generates the rotator control signal based on the phase adjust signal and the frequency offset signal.

26. The system of claim 1, wherein the phase sampling signal is offset in phase relative to the data sampling signal by a predetermined amount corresponding to a fraction of a symbol period of the received serial data signal.

27. The system of claim 26, wherein the phase sampling signal is offset in phase relative to the data sampling signal by one-half of a symbol period of the received serial data signal.

14. A method of recovering timing information from a received serial data signal, comprising:

(a) deriving a data sampling signal and a phase sampling signal each having an interpolated phase in response to a plurality of phase control signals, wherein the phase sampling signal is offset in phase relative to the data sampling signal by a predetermined amount;

(b) sampling the received serial data according to the data sampling signal to produce a data signal;

(c) sampling the received serial data according to the phase sampling signal to produce a phase signal;

(d) producing a phase error signal based on the data signal and the phase signal, wherein the phase error signal is indicative of a phase offset between the data sampling signal and the received serial data signal;

(e) producing a rotator control signal based on short-term error processing and long-term error processing of the phase error signal; and

(f) rotating the plurality of phase control signals and correspondingly the interpolated phase of the data sampling signal and the phase sampling signal in response to the rotator control signal.

15. The method of claim 14, wherein step (f) comprises rotating the plurality of phase control signals and correspondingly the interpolated phase of the data sampling signal and the phase sampling signal in a direction to reduce the phase offset between the received serial data signal and the data sampling signal.

16. The method of claim 14, wherein the rotator control signal is one of a phase-advance, a phase-retard, and a phase-hold signal, and step (f) further comprises:

rotating the plurality of phase control signals in a first direction to advance the interpolated phase of the data sampling signal and the phase sampling signal in response to the phase-advance signal;

rotating the plurality of phase control signals in a second direction to retard the interpolated phase of the data sampling signal and the phase sampling signal in response to the phase-retard signal; and

preventing the plurality of phase control signals and correspondingly the interpolated phase of the data sampling signal and the phase sampling signal from rotating in response to the phase-hold signal.

17. The method of claim 14, wherein each one of the plurality of phase control signals is a digital signal.

18. The method of claim 14, wherein step (f) further comprises rotating the interpolated phase of the data sampling signal and the phase sampling signal to one of a plurality of discrete phase values spanning a phase range of 360°

.

19. The method of claim 14, further comprising rotating the interpolated phase of the data sampling signal and the phase sampling signal at a rate corresponding to a frequency offset between a frequency of the data sampling signal and a frequency of the received serial data signal so as to frequency synchronize the received serial data signal to the data sampling signal.

20. The method of claim 14, wherein step (a) further comprises:

controlling individual magnitudes of a plurality of component signals having different phases responsive to the plurality of phase control signals; and

combining the plurality of component signals into the interpolated data sampling signal and the phase sampling signal.

21. The method of claim 20, wherein said controlling step further comprises controlling individual magnitudes of four component signals having successive phases separated at intervals of 90°

.

22. The method of claim 20, wherein said controlling step further comprises varying the magnitude of at least one of the plurality of component signals from a zero magnitude value to a maximum magnitude value in accordance with the plurality of phase control signals.

28. The method of claim 14, wherein:

the short-term error processing of step (e) further comprises integrating the phase error signal over a relatively short time period to generate a phase adjust signal that responds rapidly to changes in the phase offset between the data sampling signal and the received serial data signal; and

the long-term error processing of step (e) further comprises integrating the phase error signal over a relatively long time period to generate a frequency offset signal that responds slowly to changes in the phase offset between the data sampling signal and the received serial data signal.

29. The method of claim 28, further comprising implementing the short-term error processing and the long-term error processing with accumulators.

30. The method of claim 28, wherein step (e) further comprises producing the rotator control signal based on the phase adjust signal and the frequency offset signal.

31. The method of claim 14, wherein step (a) further comprises offsetting the phase sampling signal in phase relative to the data sampling signal by a predetermined amount corresponding to a fraction of a symbol period of the received serial data signal.

32. The method of claim 31, wherein step (a) further comprises offsetting the phase sampling signal in phase relative to the data sampling signal by one-half of a symbol period of the received serial data signal.