Host-fabric adapter having an efficient multi-tasking pipelined instruction execution micro-controller subsystem

• US 7,013,353 B2
• Filed: 03/30/2001
• Issued: 03/14/2006
• Est. Priority Date: 03/30/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gasbarro, Dominic J., Parthasarathy, Balaji
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US09/835,132
• Publication Number:
  US 20020191599A1
• Time in Patent Office: 1,810 Days
• Field of Search: 709/211, 709213-215, 709/212, 709/216, 710/7, 710 5- 6, 710 20- 21, 710/24, 710 62- 64, 702/216
• US Class Current: 710/7
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter may comprise at least one Micro-Engine (ME) arranged to establish connections and support data transfers, via a switched fabric, in response to work requests from a host system for data transfers; interface blocks arranged to interface the switched fabric and the host system, and send/receive work requests and/or data messages for data transfers, via the switched fabric, and configured to provide context information needed for said Micro-Engine (ME) to process work requests for data transfers, via the switched fabric, wherein the Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks in parallel in order to process data messages.

Claims

1. A host-fabric adapter, comprising:

at least one Micro-Engine (ME) arranged to establish connections and support data transfers, via a switched fabric, in response to work requests from a host system for data transfers;

interface blocks arranged to interface said switched fabric and said host system, and send/receive work requests and/or data for data transfers, via said switched fabric, and configured to provide context information needed for said Micro-Engine (ME) to process said work requests for data transfers, via said switched fabric,

wherein said Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks so as to process data for data transfers;

wherein said Micro-Engine (ME) processes multiple ME instructions in parallel, when said ME instructions are deterministic logic and arithmetic instructions by;

processing a first instruction at a first cycle in which an OpCode, source address and destination address are read from an Instruction Memory;

providing a source address to the interface blocks for the first instruction at a second cycle, and processing a second instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

when data for the first instruction is available from the interface blocks at a third cycle, providing the source address to the interface blocks for the second instruction, and processing a third instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

processing data messages from the interface blocks for the first instruction at a fourth cycle, and when data for the second instruction is available from the interface blocks, providing the source address to the interface blocks for the third instruction and processing a fourth instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

providing destination and write controls of the first instruction for the interface blocks at a fifth cycle, processing data messages from the interface blocks for the second instruction and when data for the third instruction is available from the interface blocks, providing the source address to the interface blocks for the fourth instruction and processing a fifth instruction in which the OpCode, source address and destination address are read from the Instruction Memory; and

when the first instruction is retired at a sixth cycle, providing destination and write controls of the second instruction for the interface blocks, processing the data from the interface blocks for the third instruction, and when data for the fourth instruction is available from the interface blocks, providing the source address to the interface blocks for the fifth instruction and processing a sixth instruction in which the OpCode, source address and destination address are read from the Instruction Memory.

2. The host-fabric adapter as claimed in claim 1, wherein said Micro-Engine (ME) is configured to ensure that only latest data from the interface blocks is used and correct data is written to the interface blocks.

3. The host-fabric adapter as claimed in claim 1, wherein said interface blocks comprises:

a serial interface arranged to receive and transmit data from said switched fabric for data transfers;

a host interface arranged to receive and transmit work requests, in the form of work queue elements (WQEs), from said host system for data transfers;

a context memory arranged to store context information needed for said Micro-Engine (ME) to process work requests for data transfers;

a first-in/first-out (FIFO) interface arranged to receive data from said switched fabric via said serial interface, and to transmit data to said switched fabric via said serial interface;

an address translation interface arranged for address translation from said Micro-Engine (ME);

a local bus interface arranged to support system accessible context connections and data transfers; and

a completion queue/doorbell manager interface arranged to provide an interface to completion queues, and to update the context information needed for said Micro-Engine (ME) to process work requests for data transfers.

4. The host-fabric adapter as claimed in claim 1, wherein said Micro-Engine (ME) comprises:

one or more Data Multiplexers arranged to supply appropriate interface data based on an ME instruction;

an Instruction Memory arranged to provide said ME instruction based on downloadable MicroCode;

an Arithmetic Logic Unit (ALU) arranged to perform mathematical, logical and shifting operations, and supply write data to a host interface, an address translation interface, a context memory interface, a local bus interface, a completion queue/doorbell manager interface, and a FIFO interface, via a system data bus; and

an Instruction Decoder arranged to supply system controls to the host interface, the address translation interface, the context memory interface, the local bus interface, the completion queue/doorbell manager interface, and the FIFO interface, via a system control bus, to execute said ME instruction from said Instruction Memory to control operations of said Data Multiplexers, and to determine functions of said Arithmetic Logic Unit (ALU).

5. The host-fabric adapter as claimed in claim 4, wherein said Instruction Memory corresponds to a random-access-memory (RAM) provided to store MicroCode that are downloadable for providing said ME instruction to said Instruction Decoder.

6. The host-fabric adapter as claimed in claim 5, wherein said Micro-Engine (ME) and said interface blocks are implemented as part of an Application Specific Integrated Circuit (ASIC).

7. A host-fabric adapter, comprising:

at least one Micro-Engine (ME) arranged to establish connections and support data transfers, via a switched fabric, in response to work requests from a host system for data transfers;

interface blocks arranged to interface said switched fabric and said host system, and send/receive work requests and/or data for data transfers, via said switched fabric, and configured to provide context information needed for said Micro-Engine (ME) to process said work requests for data transfers, via said switched fabric,

wherein said Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks so as to process data for data transfers;

wherein said Micro-Engine (ME) processes multiple ME instructions in parallel, when said ME instructions are non-deterministic logic and arithmetic instructions by;

processing a first instruction at a first cycle in which an OpCode, source address and destination address are read from an Instruction Memory;

providing the source address to the interface blocks for the first instruction at a second cycle, and processing a second instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

when data for the first instruction is available from the interface blocks at a third cycle, and a conditional Jump instruction based on Flags is set for the first instruction, processing a third instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

processing data from the interface blocks for the first instruction at a fourth cycle, providing the source address to the interface blocks for the third instruction processing a fourth instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

when data for the third instruction is available from the interface blocks at a fifth cycle, providing destination and write controls of the fourth instruction for the interface blocks;

if the Jump condition is not TRUE, processing a fifth instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

if the Jump condition is TRUE, processing the conditional Jump instruction in which the OpCode, source address and destination address are read from the Instruction Memory corresponding to a Jump Address;

when the first instruction is retired at a sixth cycle, flushing the third instruction and data for the fourth instruction available from the interface blocks, and providing the source address to the interface blocks for the conditional Jump instruction corresponding to the Jump Address if the Jump condition is TRUE; and

if the Jump condition is FALSE, providing the source address to the interface blocks for the fifth instruction and processing the conditional Jump instruction in which the OpCode, source address and destination address are read from the Instruction Memory corresponding to the Jump Address.

8. The host-fabric adapter as claimed in claim 7, wherein said Micro-Engine (ME) is configured to ensure that only latest data from the interface blocks is used and correct data is written to the interface blocks.

9. The host-fabric adapter as claimed in claim 7, wherein said Micro-Engine (ME) comprises:

one or more Data Multiplexers arranged to supply appropriate interface data based on an ME instruction;

an Instruction Memory arranged to provide said ME instruction based on downloadable MicroCode;

an Arithmetic Logic Unit (ALU) arranged to perform mathematical, logical and shifting operations, and supply write data to a host interface, an address translation interface, a context memory interface, a local bus interface, a completion queue/doorbell manager interface, and a FIFO interface, via a system data bus; and

an Instruction Decoder arranged to supply system controls to the host interface, the address translation interface, the context memory interface, the local bus interface, the completion queue/doorbell manager interface, and the FIFO interface, via a system control bus, to execute said ME instruction from said Instruction Memory to control operations of said Data Multiplexers, and to determine functions of said Arithmetic Logic Unit (ALU).

10. The host-fabric adapter as claimed in claim 9, wherein the Instruction Memory corresponds to a random-access-memory (RAM) provided to store MicroCode that are downloadable for providing the ME instruction to the Instruction Decoder.

11. The host-fabric adapter as claimed in claim 10, wherein the Micro-Engine (ME) and the appropriate interface are implemented as part of an Application Specific Integrated Circuit (ASIC).

12. A host-fabric adapter, comprising:

at least one Micro-Engine (ME) arranged to establish connections and support data transfers, via a switched fabric, in response to work requests from a host system for data transfers;

interface blocks arranged to interface said switched fabric and said host system, and send/receive work requests and/or data for data transfers, via said switched fabric, and configured to provide context information needed for said Micro-Engine (ME) to process said work requests for data transfers, via said switched fabric,

wherein said Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks so as to process data for data transfers;

wherein said Micro-Engine (ME) processes multiple tasks in parallel by;

processing a first instruction at a first cycle in which an OpCode, source address and destination address are read from an Instruction Memory;

providing the source address to the interface blocks for the first instruction at a second cycle, and processing a second instruction indicating a Task Switching Instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

when data for the first instruction is available from the interface blocks and there is no data processing at a third cycle, processing a third instruction for a new task in which the OpCode, source address and destination address are read from the Instruction Memory;

processing data for the first instruction from the interface blocks at a fourth cycle and providing the source address to the interface blocks for the third instruction for the new task;

providing destination and write controls of the first instruction for the interface blocks at a fifth cycle and, when data for the new task for the third instruction is available from the interface blocks, providing the source address to the interface blocks for a fourth instruction and processing a fifth instruction for the new task in which the OpCode, source address and destination address are read from the Instruction Memory;

when the first instruction is retired at a sixth cycle, processing data from the interface blocks for the third instruction for the new task, and when data for the new task for the fourth instruction is available from the interface blocks, providing the source address to the interface blocks for the fifth instruction and processing a sixth instruction for the new task in which the OpCode, source address and destination address are read from the Instruction Memory; and

when the second instruction is retired at a seventh cycle, providing destination and write controls for the interface blocks for the third instruction, processing data from the interface blocks for the fourth instruction for the new task, and when data for the new task for the fifth instruction is available from the interface blocks, providing the source address to the interface blocks for the sixth instruction and processing a seventh instruction for the new task in which the OpCode, source address and destination address are read from the Instruction Memory.

13. The host-fabric adapter as claimed in claim 12, wherein said Micro-Engine (ME) is configured to ensure that only latest data from the interface blocks is used and correct data is written to the interface blocks.

14. The host-fabric adapter as claimed in claim 12, wherein said Micro-Engine (ME) comprises:

one or more Data Multiplexers arranged to supply appropriate interface data based on an ME instruction;

an Instruction Memory arranged to provide said ME instruction based on downloadable MicroCode;

an Arithmetic Logic Unit (ALU) arranged to perform mathematical, logical and shifting operations, and supply write data to a host interface, an address translation interface, a context memory interface, a local bus interface, a completion queue/doorbell manager interface, and a FIFO interface, via a system data bus; and

an Instruction Decoder arranged to supply system controls to the host interface, the address translation interface, the context memory interface, the local bus interface, the completion queue/doorbell manager interface, and the FIFO interface, via a system control bus, to execute said ME instruction from said Instruction Memory to control operations of said Data Multiplexers, and to determine functions of said Arithmetic Logic Unit (ALU).

15. The host-fabric adapter as claimed in claim 14, wherein said Micro-Engine (ME) and said appropriate interface are implemented as part of an Application Specific Integrated Circuit (ASIC).

16. A host-fabric adapter installed at a host system for connecting to a switched fabric of a data network, comprising:

at least one Micro-Engine (ME) arranged to establish connections and support data transfers via said switched fabric;

a serial interface arranged to receive and transmit data from said switched fabric for data transfers;

a host interface arranged to receive and transmit work requests from said host system for data transfers; and

a context memory interface arranged to store context information needed for said Micro-Engine (ME) to process work requests for data transfers,

wherein said Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks in parallel so as to process data for data transfers;

wherein said Micro-Engine (ME) processes multiple ME instructions in parallel, when said ME instructions are deterministic logic and arithmetic instructions by;

processing a first instruction at a first cycle in which an OpCode, source address and destination address are read from an Instruction Memory;

providing a source address to the interface blocks for Instruction #1 at a second cycle, and processing a second instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

when data for the first instruction is available from the interface blocks at a third cycle, providing the source address to the interface blocks for the second instruction, and processing a third instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

processing data messages from the interface blocks for the first instruction at a fourth cycle, and when data for the second instruction is available from the interface blocks, providing the source address to the interface blocks for the third instruction and processing a fourth instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

providing destination and write controls of the first instruction for the interface blocks at a fifth cycle, processing data messages from the interface blocks for the second instruction, and when data for the third instruction is available from the interface blocks, providing the source address to the interface blocks for the fourth instruction and processing a fifth instruction in which the OpCode, source address and destination address are read from the Instruction Memory; and

when the first instruction is retired at a sixth cycle, providing destination and write controls of the second instruction for the interface blocks, processing the data from the interface blocks for the third instruction, and when data for the fourth instruction is available from the interface blocks, providing the source address to the interface blocks for the fifth instruction and processing a sixth instruction in which the OpCode, source address and destination address are read from the Instruction Memory.

17. The host-fabric adapter as claimed in claim 16, wherein said Micro-Engine (ME) is configured to ensure that only latest data from the interface blocks is used and correct data is written to the interface blocks.

18. A host-fabric adapter installed at a host system for connecting to a switched fabric of a data network, comprising:

at least one Micro-Engine (ME) arranged to establish connections and support data transfers via said switched fabric;

a serial interface arranged to receive and transmit data from said switched fabric for data transfers;

a host interface arranged to receive and transmit work requests from said host system for data transfers; and

a context memory interface arranged to store context information needed for said Micro-Engine (ME) to process work requests for data transfers,

wherein said Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more MB instructions and/or one or more tasks in parallel so as to process data for data transfers;

wherein said Micro-Engine (ME) processes multiple ME instructions in parallel, when said ME instructions are non-deterministic logic and arithmetic instructions by;

processing a first instruction at a first cycle in which an OpCode, source address and destination address are read from an Instruction Memory;

providing the source address to the interface blocks for the first instruction at a second cycle, and processing a second instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

when data for the first instruction is available from the interface blocks at a third cycle, and a conditional Jump instruction based on Flags is set for the first instruction, processing a third instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

processing data from the interface blocks for the first instruction at a fourth cycle, providing the source address to the interface blocks for the third instruction, processing a fourth instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

when data for the third instruction is available from the interface blocks at a fifth cycle, providing destination and write controls of the fourth instruction for the interface blocks;

if the Jump condition is not TRUE, processing a fifth instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

if the Jump condition is TRUE, processing the conditional Jump instruction in which the OpCode, source address and destination address are read from the Instruction Memory corresponding to a Jump Address;

when the first instruction is retired at a sixth cycle, flushing the third instruction and data for the fourth instruction available from the interface blocks, and providing the source address to the interface blocks for the conditional Jump instruction corresponding to the Jump Address if the Jump condition is TRUE; and

if the Jump condition is FALSE, providing the source address to the interface blocks for the fifth instruction and processing the conditional Jump instruction in which the OpCode, source address and destination address are read from the Instruction Memory corresponding to the Jump Address.

19. The host-fabric adapter as claimed in claim 18, wherein said Micro-Engine (ME) is configured to ensure that only latest data from the interface blocks is used and correct data is written to the interface blocks.

20. A host-fabric adapter installed at a host system for connecting to a switched fabric of a data network, comprising:

at least one Micro-Engine (ME) arranged to establish connections and support data transfers via said switched fabric;

a serial interface arranged to receive and transmit data from said switched fabric for data transfers;

a host interface arranged to receive and transmit work requests from said host system for data transfers; and

a context memory interface arranged to store context information needed for said Micro-Engine (ME) to process work requests for data transfers,

wherein said Micro-Engine (ME) is implemented with a pipelined instruction execution architecture to handle one or more ME instructions and/or one or more tasks in parallel so as to process data for data transfers;

wherein said Micro-Engine (ME) processes multiple tasks in parallel by;

processing a first instruction at a first cycle in which an OpCode, source address and destination address are read from an Instruction Memory;

providing the source address to the interface blocks for the first instruction at a second cycle, and processing a second instruction indicating a Task Switching Instruction in which the OpCode, source address and destination address are read from the Instruction Memory;

when data for the first instruction is available from the interface blocks and there is no data processing at a third cycle, processing a third instruction for a new task in which the OpCode, source address and destination address are read from the Instruction Memory;

processing data for the first instruction from the interface blocks at a fourth cycle and providing the source address to the interface blocks for the third instruction for the new task;

providing destination and write controls of the first instruction for the interface blocks at a fifth cycle and, when data for the new task for the third instruction is available from the interface blocks, providing the source address to the interface blocks for a fourth instruction and processing a fifth instruction for the new task in which the OpCode, source address and destination address are read from the Instruction Memory;

when the first instruction is retired at a sixth cycle, processing data from the interface blocks for the third instruction for the new task, and when data for the new task for the fourth instruction is available from the interface blocks, providing the source address to the interface blocks for the fifth instruction and processing a sixth instruction for the new task in which the OpCode, source address and destination address are read from the Instruction Memory; and

when the second instruction is retired at a seventh cycle, providing destination and write controls for the interface blocks for the third instruction, processing data from the interface blocks for the fourth instruction for the new task, and when data for the new task for the fifth instruction is available from the interface blocks, providing the source address to the interface blocks for the sixth instruction and processing a seventh instruction for the new task in which the OpCode, source address and destination address are read from the Instruction Memory.

21. The host-fabric adapter as claimed in claim 20, wherein said Micro-Engine (ME) is configured to ensure that only latest data from the interface blocks is used and correct data is written to the interface blocks.

22. The host-fabric adapter as claimed in claim 20, wherein said Micro-Engine (ME) comprises:

one or more Data Multiplexers arranged to supply appropriate interface data based on an ME instruction;

an Instruction Memory arranged to provide said ME instruction based on downloadable MicroCode;

an Arithmetic Logic Unit (ALU) arranged to perform mathematical, logical and shifting operations, and supply write data to a host interface an address translation interface a context memory interface a local bus interface, a completion queue/doorbell manager interface, and a FIFO interface, via a system data bus; and

an Instruction Decoder arranged to supply system controls to the host interface, the address translation interface, the context memory interface, the local bus interface, the completion queue/doorbell manager interface, and the FIFO interface, via a system control bus, to execute said ME instruction from said Instruction Memory to control operations of said Data Multiplexers, and to determine functions of said Arithmetic Logic Unit (ALU).

23. The host-fabric adapter as claimed in claim 22, wherein the Instruction Memory corresponds to a random-access-memory (RAM) provided to store MicroCode that are downloadable for providing the ME instruction to the Instruction Decoder.

24. The host-fabric adapter as claimed in claim 23 wherein the Micro-Engine (ME) and the appropriate interface are implemented as part of an Application Specific Integrated Circuit (ASIC).