System chip synthesis

• US 7,013,438 B1
• Filed: 11/01/2001
• Issued: 03/14/2006
• Est. Priority Date: 11/01/2000
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Saldanha, Alexander, Mehrotra, Amit, Higgins, Joe
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEVIN, NAUM B
• Application Number:
  US10/002,034
• Time in Patent Office: 1,594 Days
• Field of Search: 716/2, 716 4- 14, 716 17- 18, 326 39- 41
• US Class Current: 716/104
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A technique to design deep sub-micron (DSM) integrated circuits is disclosed, in which global wire delays are minimized first, before performing logic synthesis. According to the present method, a designer performs layout of physical blocks by estimating an area for each block. After connecting the pins of the blocks with no timing constraints, each wire is assigned to a metal layer, based on length. The delay of each wire is minimized by inserting buffers at optimal distances. The blocks are then partitioned into “cores” and “shells.” The shells and cores are synthesized, and then recombined. This procedure greatly reduces the number of design iterations required to complete a design.

Claims

1. A method for synthesizing an integrated circuit design, the method comprising:

performing a physical optimization of a block and wire placement, before performing a logic synthesis;

partitioning the blocks into cores and shells;

synthesizing the shells and cores; and

recombining the cores and shells into blocks

wherein;

a core comprises logic in a block bounded by registers; and

a shell comprises logic between a core and pins of a block.

2. The method of claim 1, wherein performing physical optimization of block placement comprises estimating an area of each block.

3. The method of claim 2, wherein performing physical optimization of wire placement comprises determining a pin assignment layout.

4. The method of claim 3, wherein performing physical optimization of wire placement further comprises selecting a layer for each wire based on wire length.

5. The method of claim 4, wherein performing physical optimization of wire placement further comprises minimizing a delay in each wire by inserting buffers at optimal distances.

6. The method of claim 5, wherein synthesizing the shells comprises determining a proportion of time to assign to each shell on each side of a wire.

7. The method of claim 5, wherein after synthesizing the shells, the process of performing physical optimization of blocks and wires and partitioning the blocks is incrementally repeated if the wire delays are too long for shell synthesis.

8. The method according to claim 1, wherein the method is codified as instructions on a computer readable media, that, when loaded into a computer, cause the computer to perform the steps of the method.

9. A method for designing deep sub-micron integrated circuits, the method comprising:

performing a layout of physical blocks by estimating an area for each block;

connecting pins of the blocks with no timing constraints;

assigning each wire to a metal layer pair;

optimizing the speed of each wire for its respective layer;

partitioning the blocks into cores comprising logic in a block bounded by registers and shells comprising logic between a core and pins of the block;

synthesizing the shells;

synthesizing the cores; and

recombining the shells and cores.

10. The method of claim 9, wherein each wire is assigned to a metal layer based on a relative length of the wire.

11. The method of claim 10, wherein optimizing the speed of each wire comprises minimizing a delay in each wire by inserting buffers at optimal distances.

12. The method of claim 11, wherein synthesizing the shells comprises determining a proportion of time to assign to each shell on each side of a wire.

13. The method of claim 12, wherein after synthesizing the shells, the layout procedure is incrementally repeated if the wire delays are too long for shell synthesis.

14. A method for reducing a design cycle time for integrated circuits, the method comprising:

laying out blocks by estimating an area for each block;

minimizing a delay in each global wire;

partitioning each block into a core of logic bounded by registers and a shell of logic between the core and pins of the block;

performing a logic synthesis on each shell by utilizing a known delay for each wire;

performing logic synthesis on each core; and

recombining the shells and cores.

15. The method of claim 14, wherein minimizing a delay in each global wire comprises assigning each wire to a layer, and inserting buffers at optimal distances.

16. The method of claim 15, wherein performing logic synthesis on each shell comprises determining a proportion of time to assign to each shell on each side of a wire.

17. The method of claim 16, wherein after synthesizing the shells, the layout procedure is incrementally repeated if the wire delays are too long for shell synthesis.

18. A method for synthesizing an integrated circuit design, the method comprising:

performing a physical optimization of a block and wire placement, before performing a logic synthesis;

partitioning the blocks into cores and shells;

synthesizing the shells and cores; and

recombining the cores and shells into blocks;

wherein;

performing the physical optimization of the wire placement comprises determining a pin assignment layout;

performing the physical optimization of the wire placement further comprises selecting a layer for each wire based on wire length;

performing the physical optimization of the wire placement further comprises minimizing a delay in each wire by inserting buffers at optimal distances;

each wire is overdesigned in that it is designed to be as fast as possible at the earliest stages of design and wire changes related to wire speed in subsequent design stages comprise area recovery by dropping repeaters that are not absolutely necessary; and

synthesizing the shells comprises determining a proportion of time to assign to each shell on each side of a wire wherein each core is logic bounded by registers in a block and each shell is logic between a core and pins of a block.

19. The method according to claim 18, wherein the step of performing physical optimization of block and wire placement is performed without concern for wire delays.

20. The method according to claim 18, wherein the only estimation utilized in the method is a block size estimation, and the block size is adjusted and the method is re-iterated based on the adjusted block size.

21. The method according to claim 18, further comprising the steps of connecting pins without timing constraints, and assigning layers to wires qualitatively based on wirelength without regard to timing.

22. The method according to claim 18, wherein the entire design process is performed without iterations due to timing constraints of any wires.

23. The method according to claim 18, wherein wire changes related to wire speed in subsequent design stages comprise one of changing layers of the wires and area recovery performed by dropping buffers that are not absolutely necessary.