Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
First Claim
1. A method for processing an integrated circuit layout, said method comprising:
- determining legal swaps and moves of circuit modules for a local area of said integrated circuit layout; and
calculating an associated design cost for each legal swap and move, wherein said associated design cost considers the potential use of non-Manhattan routes being defined in a later routing operation; and
performing a swap or move if said associated design cost for said swap or move is less than a current design cost and repeating said steps of determining, calculating, and performing until no significant design cost improvement is achieved.
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Abstract
The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.
173 Citations
18 Claims
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1. A method for processing an integrated circuit layout, said method comprising:
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determining legal swaps and moves of circuit modules for a local area of said integrated circuit layout; and calculating an associated design cost for each legal swap and move, wherein said associated design cost considers the potential use of non-Manhattan routes being defined in a later routing operation; and performing a swap or move if said associated design cost for said swap or move is less than a current design cost and repeating said steps of determining, calculating, and performing until no significant design cost improvement is achieved. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer readable medium, said computer readable medium comprising a set of computer instructions for processing an integrated circuit layout, said computer instructions implementing the steps of:
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determining legal swaps and moves of circuit modules for a local area of said integrated circuit layout; and calculating an associated design cost for each legal swap and move, wherein said associated design cost considers the potential use of non-Manhattan routes being defined in a later routing operation; and
performing a swap or move if said associated design cost for said swap or move is less than a current design cost and repeating said steps of determining, calculating, and performing until no significant design cost improvement is achieved. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification
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- Resources
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Current AssigneeCadence Design Systems Incorporated (Cadence Group)
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Original AssigneeCadence Design Systems Incorporated (Cadence Group)
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InventorsTeig, Steven, Wang, Maogang
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Primary Examiner(s)Whitmore, Stacy A.
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Assistant Examiner(s)TAT, BINH C
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Application NumberUS10/334,645Time in Patent Office1,169 DaysField of Search716 1- 18US Class Current716/123CPC Class CodesG06F 30/392 Floor-planning or layout, e...
