Semiconductor light emitting device and method

• US 7,015,054 B2
• Filed: 11/10/2003
• Issued: 03/21/2006
• Est. Priority Date: 12/22/1999
• Status: Expired due to Fees

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Lumileds Lighting US LLC (Apollo Global Management, Inc.)
• Inventors: Krames, Michael R., Steigerwald, Daniel A.
• Primary Examiner(s): Graybill, David E.
• Application Number:
  US10/705,156
• Publication Number:
  US 20040094774A1
• Time in Patent Office: 862 Days
• Field of Search: 438/22, 438/26, 438/29, 438/33
• US Class Current: 438/22
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 33/02 characterised by the semiconductor bodies
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/64 Heat extraction or cooling elements
• CPC Class Codes: H01L 33/641 characterized by the materials

Abstract

A light-emitting device includes: a semiconductor structure formed on one side of a substrate, the semiconductor structure having a plurality of semiconductor layers and an active region within the layers; and first and second conductive electrodes contacting respectively different semiconductor layers of the structure; the substrate comprising a material having a refractive index n>2.0 and light absorption coefficient α, at the emission wavelength of the active region, of α>3 cm⁻¹. In a preferred embodiment, the substrate material has a refractive index n>2.3, and the light absorption coefficient, α, of the substrate material is α<1 cm⁻¹.

Claims

1. A method for making semiconductor light emitting device chips, comprising the steps of:

providing a substrate of substantially transparent silicon carbide;

forming a semiconductor structure on one side of said substrate, said semiconductor structure having a plurality of semiconductor layers and an active region within said layers;

applying electrodes to semiconductor layers of said structure on said one side of said substrate to four semiconductor light emitting devices; and

dicing said substrate and devices into a plurality of chips

wherein said substrate has a refractive index n>

2.3 and a light absorption coefficient α

, at an emission wavelength of said active region, of α

<

3 cm<sup>−

1</sup>.

2. The method as defined by claim 1, further comprising bonding the electrodes of each device chip to a submount to obtain inverted semiconductor light emitting devices.

3. The method as defined by claim 1, wherein said step of dicing includes sawing of said substrate and devices into a plurality of chips.

4. The method as defined by claim 1, wherein said step of providing a substrate comprises providing a substrate of polycrystalline silicon carbide.

5. The method as defined by claim 1, wherein said step of providing a substrate comprises providing a substrate of polycrystalline silicon carbide having single crystal silicon carbide thereon.

6. The method as defined by claim 1, wherein said step of dicing into chips comprises dicing into chips having at least one dimension perpendicular to thickness that is less than 400 μ

m.

7. The method as defined by claim 1, wherein said step of dicing into chips comprises dicing into chips having dimensions perpendicular to thickness that are less than 400×

400 μ

m.

8. The method as defined by claim 1, wherein step of dicing into chips comprises dicing into chips having an area less than 0.16 mm².

9. The method as defined by claim 1, wherein said step of dicing into chips comprises dicing into chips having at least one dimension perpendicular to thickness that is less than 300 μ

m.

10. The method as defined by claim 1, wherein said step of dicing into chips comprises dicing into chips having dimensions perpendicular to thickness that are less than 300×

300 μ

m.

11. The method as defined by claim 1, wherein step of dicing into chips comprises dicing into chips having an area less than 0.09 mm².

12. The method as defined by claim 1, wherein said step of forming a semiconductor structure having a plurality of layers comprises providing a plurality of layers including an n-type layer of a III-nitride semiconductor and a p-type layer of a III-nitride semiconductor on opposing sides of said active region.

13. The method as defined by claim 9, wherein said step of forming a semiconductor structure having a plurality of layers comprises providing a plurality of layers including an n-type layer of a III-nitride semiconductor and a p-type layer of a III-nitride semiconductor on opposing sides of said active region.