Cloverleaf microgyroscope with through-wafer interconnects and method of manufacturing a cloverleaf microgyroscope with through-wafer interconnects

• US 7,015,060 B1
• Filed: 12/08/2004
• Issued: 03/21/2006
• Est. Priority Date: 12/08/2004
• Status: Expired due to Fees

• Current Assignee: HRL Laboratories LLC (The Boeing Co.)
• Original Assignee: HRL Laboratories LLC (The Boeing Co.)
• Inventors: Stratton, Frederic P., Kubena, Randall L., Chang, David T.
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US11/008,721
• Time in Patent Office: 468 Days
• Field of Search: 438 48- 53, 438455-465, 216/2, 7350402-50416
• US Class Current: 438/50
• CPC Class Codes: G01C 19/5719 using planar vibrating masses driven in a translation vibration along an axis
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate

Abstract

The present invention relates to a method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising: attaching a post wafer to a resonator wafer, forming a bottom post from the post wafer being attached to the resonator wafer, preparing a base wafer with through-wafer interconnects, attaching the resonator wafer to the base wafer, wherein the bottom post fits into a post hole in the base wafer, forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis, and attaching a cap wafer on top of the base wafer.

Claims

1. A method of manufacturing a cloverleaf microgyroscope containing an integrated post comprising:

a) attaching a post wafer to a resonator wafer,

b) forming a bottom post from the post wafer,

c) preparing a base wafer with through-wafer interconnects,

d) attaching the resonator wafer to the base wafer, wherein the bottom post fits into a post hole in the base wafer,

e) forming a top post from the resonator wafer, wherein the bottom and top post are formed symmetrically around the same axis, and

f) attaching a cap wafer on top of the base wafer.

2. The method according to claim 1, wherein the through-wafer interconnects comprise copper, copper alloys and mixtures thereof.

3. The method according to claim 1, wherein the top post is formed of a bulk silicon base having a thickness of ≦

500 μ

m, a silicon dioxide layer of ≦

2 μ

m and a heavily-doped Silicon epi-layer of 10 μ

m–

20 μ

m, p-type, 1e19–

1e20 cm<sup>−

3</sup>.

4. The method according to claim 1, wherein the bottom post is formed of a bulk silicon base having a thickness of ≦

500 μ

m and a silicon dioxide layer of ≦

2 μ

m.

5. The method according to claim 1, wherein the base wafer is manufactured of substrate containing moderately doped silicon substrate p-type, 1e19 cm⁻

3 with a thickness of about ≦

800 μ

m.

6. The method according to claim 1, wherein ohmic contacts and interconnect metals containing Al or Al/Ti are formed preferably on the base wafer before the resonator wafer is attached to the base wafer.

7. The method according to claim 1, wherein electrodes, bond pad, and wire bond metal are formed on the base wafer before the resonator wafer is attached to the base wafer.

8. The method according to claim 1, wherein electrodes, bond pad, and wire bond metal are formed on the base wafer before the resonator wafer is attached to the base wafer.

9. The method according to claim 1, wherein a seal ring containing Ti/Pt/Au is formed on the base wafer before the resonator wafer is attached to the base wafer.

10. The method according to claim 1, wherein the cap wafer is manufactured of lightly doped bulk silicon having a thickness of ≦

800 μ

m.

11. The method according to claim 1, wherein an opening is prepared in the cap wafer, a wire is led through the opening in the cap wafer and bonded to a bonding pad on the base wafer.

12. The method according to claim 1, wherein parts of heavily doped silicon layer of the resonator wafer are removed by resist lithography and photoresist removal.

13. The method according to claim 1, wherein the bondage between heavily-doped silicon epi-layer of the resonator and silicon dioxide layer of the post wafer is achieved by heating at a temperature from 800°

C. to 1000°

C.

14. The method according to claim 1, wherein bulk silicon layer and silicon dioxide of the post wafer are partially removed to yield the bottom post by resist lithography, CF₄/O₂ plasma etch SiO₂ and removal of photoresist.

15. The method according to claim 1, wherein the bonding of the resonator wafer to the base wafer is carried out by an Au to Au thermo-compression bonding at a temperature from 200°

C. to 500°

C.

16. The method according to claim 1, wherein a bulk silicon layer and silicon dioxide of the resonator wafer are partially removed to yield a top post by resist lithography, CF₄/O₂ plasma etch of SiO₂ and removal of photoresist.

17. The method according to claim 1, wherein the bondage between the cap wafer and the base wafer is carried out with solder metal at a temperature at about 100°

C. to 300°

C.

18. The method according to claim 1, wherein a hole in the cap wafer is formed by wet etch of silicon and vacuum oven baking.

19. The method according to claim 1, wherein the wire bonding is carried out by saw cutting of cap wafer and ball bonding of wires to wire bonding pad of the base wafer.