Method of forming silicided gate structure

• US 7,015,126 B2
• Filed: 06/03/2004
• Issued: 03/21/2006
• Est. Priority Date: 06/03/2004
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Cheng-Tung, Chang, Chih-Wei, Shue, Shau-Lin, Wu, Chii-Ming, Wang, Mei-Yun
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/859,730
• Publication Number:
  US 20050272235A1
• Time in Patent Office: 656 Days
• Field of Search: 438/592, 438/655, 438/664, 438/682, 438/595, 438/649, 438/651, 257/384, 257/412
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

Claims

1. A method of forming a silicided gate of a field effect transistor on a substrate having active regions, comprising the steps of:

(a) forming a shielding layer over said substrate, including over said active regions, said shielding layer having an opening therein to expose a surface of said gate electrode;

(b) fully siliciding said gate electrode, wherein said shielding layer prevents formation of said silicide in said active regions during step (b);

(c) after step (b), depositing a metal over the active regions and said gate electrode; and

(d) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

2. The method of claim 1, wherein said shielding layer is conformally formed over said substrate, including over said gate, said method further comprising the step of etching said opening in said shielding layer to expose said surface of said gate.

3. The method of claim 1, wherein said shielding layer has a thickness between about 30–

1000 Å

.

4. The method of claim 3, wherein said shielding layer comprises SiO2, SiN, SiC, SiCN or SiON.

5. The method of claim 1, wherein step (b) comprises:

conformally depositing a layer of metal over said substrate, including over said shielding layer and said exposed surface of said gate electrode; and

annealing to form said silicide in said gate electrode,

wherein the shielding layer prevents said metal deposited over said shielding layer from reacting with the active regions during said annealing step.

6. The method of claim 5, wherein said metal layer deposited over said shielding layer is selected from the group consisting of Co/Ti, Co/TiN, Ni/Ti and Ni/TiN.

7. The method of claim 1, wherein said shielding layer is conformally formed over said substrate, including over said gate, said method further comprising the step of forming said opening in said shielding layer to expose said surface of said gate.

8. The method of claim 1, further comprising, after step (b) and before step (c) removing said shielding layer from over said active regions.

9. The method of claim 1, wherein the metal layer deposited in step (c) is selected from the group consisting of Co/Ti, Co/TiN, Ni/Ti and Ni/TiN.

10. The method of claim 1, wherein the height of the gate is between about 500–

2000 Å

.

11. The method of claim 1, wherein the silicide formed in the gate and active regions comprises Co, Ni or Ti.

12. The method of claim 1, wherein said gate silicide comprises a first metal silicide formed from a first metal and said silicide in said active regions comprises a second metal silicide formed from a second metal different from said first metal.

13. A method of forming a silicided gate of a field effect transistor on a substrate having active regions, comprising the steps of:

conformally depositing a shielding layer over the active regions and gate, wherein said gate comprises silicon, said gate having sidewall spacers formed adjacent thereto, said shielding layer being formed over said sidewall spacers;

etching an opening in said shielding layer to expose a top surface of said gate;

depositing a first metal layer over said substrate, including on said exposed surface of said gate;

annealing to cause said first metal to react with said gate, wherein said gate is fully silicided, wherein said shielding layer prevents formation of said silicide in said active regions during said annealing step;

removing unreacted portions of said first metal layer;

removing remaining portions of said shielding layer;

depositing a second metal over said substrate, including over said active regions and said gate; and

annealing to cause said second metal to react with said active regions to form silicide therein, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

14. The method of claim 13, wherein said shielding layer has a thickness between about 30–

1000 Å

.

15. The method of claim 14, wherein said shielding layer comprises SiO2, SiN, SiC, SiCN or SiON.

16. The method of claim 13, wherein said first and second metals are selected from the group consisting of Co/Ti, Co/TiN, Ni/Ti and Ni/TiN.

17. The method of claim 13, wherein the height of the gate is between about 500–

2000 Å

.

18. The method of claim 13, wherein the silicide formed in the gate and active regions comprises Co, Ni or Ti.

19. The method of claim 13, wherein said gate silicide comprises a first metal silicide formed from a first metal and said silicide in said active regions comprises a second metal suicide formed from a second metal different from said first metal.