Nonvolatile semiconductor memory cell and method of manufacturing the same

• US 7,015,539 B2
• Filed: 03/04/2004
• Issued: 03/21/2006
• Est. Priority Date: 01/05/2004
• Status: Expired due to Fees

• Current Assignee: Cleveland Clinic Foundation, Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US10/791,870
• Publication Number:
  US 20050145925A1
• Time in Patent Office: 747 Days
• Field of Search: 257/317, 257/315
• US Class Current: 257/317
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer. Gate side-wall insulation films are formed on both side surfaces of the stacked-gate structure. The thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side. The width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side.

Claims

1. A nonvolatile semiconductor memory cell comprising:

a semiconductor substrate;

a stacked-gate structure that includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on the semiconductor substrate, the inter-electrode insulation film having a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer; and

gate side-wall insulation films formed on both side surfaces of the stacked-gate structure,

wherein a thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side, and the width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side,

wherein a width (Q) of the floating gate electrode in the channel length direction is 50 nm or less on a surface of the tunnel insulation film, and a distance (S) between an end portion of one of the gate side-wall insulation films, which end portion is located on a side opposed to the floating gate electrode, and an end portion of the other gate side-wall insulation film, which end portion is located on a side opposed to the floating gate electrode, is 1.3 or more times as great as the width (Q) of the floating gate electrode in the channel length direction, and

wherein a portion of the floating gate contacts the inter-electrode insulation film, and a length (P) of the portion of the floating gate satisfies;

Q<

P<

S.

2. The nonvolatile semiconductor memory cell according to claim 1, wherein the inter-electrode insulation film has as substantially flat structure, and an area of the tunnel insulation film, which contacts the floating gate electrode, is 70% or less of an area of the inter-electrode insulation film, which contacts the floating gate electrode.

3. The nonvolatile semiconductor memory cell according to claim 1, wherein the first and second oxidant barrier layers are formed of one of a silicon nitride film, a silicon oxynitride film, a titanium nitride film and a tungsten nitride film.

4. The nonvolatile semiconductor memory cell according to claim 1, wherein the gate side-wall insulation films comprise a first side-wall insulation film that is provided on a side surface of the floating gate electrode, and a second side-wall insulation film that is provided on a side surface of the control gate electrode.

5. The nonvolatile semiconductor memory cell according to claim 4, wherein the control gate electrode has a two-layer structure that comprises a high-resistance lower layer and a low-resistance upper layer.

6. The nonvolatile semiconductor memory cell according to claim 5, wherein the control gate electrode lower layer is formed of polysilicon and the control gate electrode upper layer is formed of silicide.

7. The nonvolatile semiconductor memory cell according to claim 5, wherein an area where an upper surface of the control gate electrode lower layer contacts a lower surface of the control gate electrode upper layer is substantially equal to an area where a lower surface of the control gate electrode lower layer contacts the inter-electrode insulation film.

8. The nonvolatile semiconductor memory cell according to claim 5, wherein the second side-wall insulation film is thin at upper and lower surfaces of the control gate electrode lower layer, and thick at a central part of the control gate electrode lower layer.

9. The nonvolatile semiconductor memory cell according to claim 1, wherein a device isolation insulation film is buried at a side surface of the floating gate electrode in a channel width direction.

10. A memory card comprising:

a memory chip including a plurality of nonvolatile memory cells, and a controller that controls the memory chip, the memory chip and the controller being mounted on a single wiring board,

wherein the memory cell comprises;

a stacked-gate structure that includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate, the inter-electrode insulation film having a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer; and

gate side-wall insulation films formed on both side surfaces of the stacked-gate structure;

wherein a thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side, and the width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side,

wherein a width (Q) of the floating gate electrode in the channel length direction is 50 nm or less on a surface of the tunnel insulation film, and a distance (S) between an end portion of one of the gate side-wall insulation films, which end portion is located on a side opposed to the floating gate electrode, and an end portion of the other gate side-wall insulation film, which end portion is located on a side opposed to the floating gate electrode, is 1.3 or more times as great as the width (Q) of the floating gate electrode in the channel length direction; and

wherein a portion of the floating gate contacts the inter-electrode insulation film, and a length (P) of the portion of the floating gate satisfies;

Q<

P<

S.