Push-pull output driver
First Claim
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1. A driver circuit, comprising:
- a first transistor having a source electrode and a drain electrode, the first transistor to source a current to an output terminal, wherein the source electrode of the first transistor is coupled to ground and the drain electrode in the first transistor is coupled to the output terminal;
a second transistor having a source electrode and a drain electrode, the second transistor to sink a current from the output terminal, wherein the source electrode of the second transistor is coupled to a voltage source and wherein the drain electrode in the second transistor is coupled to the output terminal;
a third transistor for pre-driving the first transistor in response to a signal applied to the third transistor through a drive signal path, wherein the drive signal path has a first delay; and
a first circuit for defining a non-overlap signal path for the signal applied to the third transistor, wherein the non-overlap signal path has a second delay, and wherein the second delay is less than the first delay.
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Abstract
An improved, open-loop push-pull driver is described. Closed-loop feedback loop techniques for control of the push-pull driver are described. These techniques are particularly well adapted to control shoot-through current in a push-pull driver circuit.
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Citations
20 Claims
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1. A driver circuit, comprising:
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a first transistor having a source electrode and a drain electrode, the first transistor to source a current to an output terminal, wherein the source electrode of the first transistor is coupled to ground and the drain electrode in the first transistor is coupled to the output terminal; a second transistor having a source electrode and a drain electrode, the second transistor to sink a current from the output terminal, wherein the source electrode of the second transistor is coupled to a voltage source and wherein the drain electrode in the second transistor is coupled to the output terminal; a third transistor for pre-driving the first transistor in response to a signal applied to the third transistor through a drive signal path, wherein the drive signal path has a first delay; and a first circuit for defining a non-overlap signal path for the signal applied to the third transistor, wherein the non-overlap signal path has a second delay, and wherein the second delay is less than the first delay. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A driver circuit, comprising:
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a first transistor having a source electrode and a drain electrode, the source electrode connected to a voltage source and the drain electrode connected to an output terminal; a second transistor having a source electrode and a drain electrode, the source electrode connected to ground and the drain electrode connected to the output terminal; and a first circuit having a first signal path, wherein the first circuit is operable in one of two modes, a first mode and a second mode, the first mode applying a signal to the first transistor and the second transistor to form a push-pull driver circuit, the signal having a first delay through the first signal path, and the second mode applying the signal to a boot-strap circuit and the second transistor to form an open-drain driver circuit.
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12. A driver circuit, comprising:
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a first transistor having a source electrode and a drain electrode, the source electrode connected to a voltage source and the drain electrode connected to an output terminal; a second transistor having a source electrode and a drain electrode, the source electrode connected to ground and the drain electrode connected to the output terminal; a first circuit having a first signal path; a second circuit having a second signal path and a corresponding second delay, wherein the second circuit increases a transition edge of an output signal in the first mode of operation and in the second mode of operation; and a third circuit, wherein the first circuit is operable in one of two modes, a first mode and a second mode, the first mode applying a signal to the first transistor and the second transistor to form a push-pull driver circuit, the signal having a first delay through the first signal path, and the second mode applying the signal to the second transistor to form an open-drain driver circuit; and wherein the third circuit is enabled in the first mode of operation to define a third signal path for the signal applied to the first transistor and the second transistor, the third signal path comprising a non-overlapped signal path and having a third delay, and wherein the third circuit is disabled in the second mode of operation. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A method of selecting a mode of operation in a driver circuit, comprising:
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applying a control signal to a circuit to select a respective mode of operation of the driver circuit, wherein in a first mode of operation the circuit applies a signal to two transistors to form a push-pull driver circuit, and wherein in a second mode of operation the circuit applies the signal to a boot-strap circuit and one transistor to form an open-drain driver circuit.
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Specification