Push-pull output driver

• US 7,015,721 B2
• Filed: 08/24/2004
• Issued: 03/21/2006
• Est. Priority Date: 12/19/2001
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Nguyen, Huy M., Vu, Roxanne, Lau, Benedict
• Primary Examiner(s): LE, DON P
• Application Number:
  US10/925,544
• Publication Number:
  US 20050057278A1
• Time in Patent Office: 574 Days
• Field of Search: 326/37, 326/38, 326 82- 90
• US Class Current: 326/83
• CPC Class Codes: H03K 17/166 Soft switching
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/01735 by bootstrapping, i.e. by positive feed-back

Abstract

An improved, open-loop push-pull driver is described. Closed-loop feedback loop techniques for control of the push-pull driver are described. These techniques are particularly well adapted to control shoot-through current in a push-pull driver circuit.

Claims

1. A driver circuit, comprising:

a first transistor having a source electrode and a drain electrode, the first transistor to source a current to an output terminal, wherein the source electrode of the first transistor is coupled to ground and the drain electrode in the first transistor is coupled to the output terminal;

a second transistor having a source electrode and a drain electrode, the second transistor to sink a current from the output terminal, wherein the source electrode of the second transistor is coupled to a voltage source and wherein the drain electrode in the second transistor is coupled to the output terminal;

a third transistor for pre-driving the first transistor in response to a signal applied to the third transistor through a drive signal path, wherein the drive signal path has a first delay; and

a first circuit for defining a non-overlap signal path for the signal applied to the third transistor, wherein the non-overlap signal path has a second delay, and wherein the second delay is less than the first delay.

2. The driver circuit of claim 1, wherein the first circuit limits shoot-through in a current path coupled to the output terminal in accordance with the first delay and the second delay.

3. The driver circuit of claim 1, wherein switching signals for the driver circuit are actively tuned using a closed feedback loop.

4. The driver circuit of claim 3, wherein active tuning of the switching signals adjusts for variations in fabrication processes for the driver circuit, operating temperature and operating voltage.

5. The driver circuit of claim 3, wherein the closed feedback loop is based on a timing relationship provided by a delay locked loop.

6. The driver circuit of claim 1, further comprising:

a second circuit defining a boot-strap signal path for the signal being applied to the third transistor, wherein the second circuit has a third delay through the boot-strap signal path, and wherein the third delay is greater than the second delay and is less than the first delay.

7. The driver circuit of claim 6, wherein the second circuit comprises:

a gate receiving an output voltage at the output terminal and generating a charge pump enable signal; and

a third circuit applying charge to the third transistor in response to the charge pump enable signal.

8. The driver circuit of claim 7, wherein the third circuit comprises a positive feedback loop.

9. The driver circuit of claim 6, wherein the second circuit only boosts a portion of an output signal transition edge.

10. The driver circuit of claim 1, further comprising a second circuit for disabling the second transistor.

11. A driver circuit, comprising:

a first transistor having a source electrode and a drain electrode, the source electrode connected to a voltage source and the drain electrode connected to an output terminal;

a second transistor having a source electrode and a drain electrode, the source electrode connected to ground and the drain electrode connected to the output terminal; and

a first circuit having a first signal path,

wherein the first circuit is operable in one of two modes, a first mode and a second mode, the first mode applying a signal to the first transistor and the second transistor to form a push-pull driver circuit, the signal having a first delay through the first signal path, and the second mode applying the signal to a boot-strap circuit and the second transistor to form an open-drain driver circuit.

12. A driver circuit, comprising:

a first transistor having a source electrode and a drain electrode, the source electrode connected to a voltage source and the drain electrode connected to an output terminal;

a second transistor having a source electrode and a drain electrode, the source electrode connected to ground and the drain electrode connected to the output terminal;

a first circuit having a first signal path;

a second circuit having a second signal path and a corresponding second delay, wherein the second circuit increases a transition edge of an output signal in the first mode of operation and in the second mode of operation; and

a third circuit,

wherein the first circuit is operable in one of two modes, a first mode and a second mode, the first mode applying a signal to the first transistor and the second transistor to form a push-pull driver circuit, the signal having a first delay through the first signal path, and the second mode applying the signal to the second transistor to form an open-drain driver circuit; and

wherein the third circuit is enabled in the first mode of operation to define a third signal path for the signal applied to the first transistor and the second transistor, the third signal path comprising a non-overlapped signal path and having a third delay, and wherein the third circuit is disabled in the second mode of operation.

13. The driver circuit of claim 12, wherein in the first mode the third circuit limits shoot-through in a current path coupled to the output terminal in accordance with the first delay and the second delay.

14. The driver circuit of claim 12, wherein switching signals for the output driver are actively tuned in the first mode of operation using a closed feedback loop.

15. The driver circuit of claim 14, wherein active tuning of the switching signals adjusts for variations in fabrication processes for the driver circuit, operating temperature and operating voltage.

16. The driver circuit of claim 14, wherein the closed feedback loop is based on a timing relationship provided by a delay locked loop.

17. The driver circuit of claim 12, wherein the third delay is less than the first delay.

18. The driver circuit of claim 12, wherein the second delay is greater than the third delay and less than the first delay.

19. The driver circuit of claim 12, wherein the second circuit only increases a portion of the transition edge of the output signal.

20. A method of selecting a mode of operation in a driver circuit, comprising:

applying a control signal to a circuit to select a respective mode of operation of the driver circuit,

wherein in a first mode of operation the circuit applies a signal to two transistors to form a push-pull driver circuit, and wherein in a second mode of operation the circuit applies the signal to a boot-strap circuit and one transistor to form an open-drain driver circuit.