Current-controlled CMOS circuits with inductive broadbanding

• US 7,015,722 B2
• Filed: 05/10/2005
• Issued: 03/21/2006
• Est. Priority Date: 02/24/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Green, Michael M.
• Primary Examiner(s): Cho, James H.
• Application Number:
  US11/125,455
• Publication Number:
  US 20050258873A1
• Time in Patent Office: 315 Days
• Field of Search: 326/83
• US Class Current: 326/83
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 2200/36 the amplifier comprising means for increasing the bandwidth
• CPC Class Codes: H03F 2203/45506 the CSC comprising only one switch
• CPC Class Codes: H03F 2203/45631 the LC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 2203/45704 the LC comprising one or more parallel resonance circuits
• CPC Class Codes: H03F 2203/7203 the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias current in the amplifier
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C³MOS logic with inductive broadbanding/C³MOS logic with low power conventional CMOS logic. The combined C³MOS logic with inductive broadbanding/C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, the MOSFET circuit comprising:

a first circuitry, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to;

receive a first plurality of signals;

process the first plurality of signals thereby generating a second plurality of signals such that each signal of the second plurality of signals has a first frequency; and

output the second plurality of signals;

a second circuitry, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic with inductive broadbanding, wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals that correspond to at least one signal of the second plurality of signals, and wherein first and second series connected RL circuits respectively couple first and second output nodes of a logic element to a power supply node, that is operable to;

receive the second plurality of signals; and

process the second plurality of signals thereby generating at least one output signal that has a second frequency.

2. The MOSFET circuit of claim 1, wherein:

the at least one output signal is a serialized signal generated from the second plurality of signals; and

the second frequency is higher than the first frequency.

3. The MOSFET circuit of claim 1, wherein:

the at least one output signal is a serialized signal generated from the second plurality of signals; and

the at least one output signal is launched into a communication channel to which the MOSFET circuit is communicatively coupled.

4. The MOSFET circuit of claim 1, further comprising:

first and second capacitive loads respectively coupled to the first and second output nodes of the logic element.

5. The MOSFET circuit of claim 1, wherein:

each RL circuit of the first and second series connected RL circuits includes a resistor and an inductor connected in series; and

the inductor of each RL circuit of the first and second series connected RL circuits is a spiral inductor coupled to the silicon substrate.

6. The MOSFET circuit of claim 1, wherein:

each RL circuit of the first and second series connected RL circuits includes a resistor and an inductor connected in series; and

the resistor of each RL circuit of the first and second series connected RL circuits is a p-channel MOSFET that operates substantially in its linear operating region.

7. The MOSFET circuit of claim 1, further comprising:

a third circuitry, implemented using C³MOS logic with inductive broadbanding, wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals that correspond to at least one serialized input signal, and wherein first and second series connected RL circuits respectively couple first and second output nodes of at least one additional logic element to at least one additional power supply node, that is operable to;

receive the at least one serialized input signal;

process the at least one serialized input signal thereby generating the first plurality of signals; and

output the first plurality of signal that is received by the first circuitry.

8. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, the MOSFET circuit comprising:

a first circuitry, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to;

receive a first plurality of signals;

process the first plurality of signals thereby generating a second plurality of signals such that each signal of the second plurality of signals has a first frequency; and

output the second plurality of signals;

a second circuitry, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic, wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals that correspond to at least one signal of the second plurality of signals, that is operable to;

receive the second plurality of signals; and

process the second plurality of signals thereby generating a third plurality of signals such that each signal of the third plurality of signals has a second frequency; and

a third circuitry, implemented using C³MOS logic with inductive broadbanding, wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals that correspond to at least one signal of the third plurality of signals, and wherein first and second series connected RL circuits respectively couple first and second output nodes of a logic element to a power supply node, that is operable to;

receive the third plurality of signals; and

process the third plurality of signals thereby generating at least one output signal that has a third frequency.

9. The MOSFET circuit of claim 8, wherein:

the at least one output signal is a serialized signal generated from the third plurality of signals;

the third frequency is higher than the second frequency; and

the second frequency is higher than the first frequency.

10. The MOSFET circuit of claim 8, wherein:

the at least one output signal is a serialized signal generated from the third plurality of signals; and

the at least one output signal is launched into a communication channel to which the MOSFET circuit is communicatively coupled.

11. The MOSFET circuit of claim 8, wherein:

first and second capacitive loads respectively coupled to the first and second output nodes of the logic element.

12. The MOSFET circuit of claim 8, wherein:

each RL circuit of the first and second series connected RL circuits includes a resistor and an inductor connected in series; and

the inductor of each RL circuit of the first and second series connected RL circuits is a spiral inductor coupled to the silicon substrate.

13. The MOSFET circuit of claim 8, wherein:

each RL circuit of the first and second series connected RL circuits includes a resistor and an inductor connected in series; and

the resistor of each RL circuit of the first and second series connected RL circuits is a p-channel MOSFET that operates substantially in its linear operating region.

14. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, the MOSFET circuit comprising:

a first circuitry, implemented using current-controlled complementary metal-oxide semiconductor (C³MOS) logic, wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals that correspond to at least one signal of a first plurality of signals, that is operable to;

receive the first plurality of signals; and

process the first plurality of signals thereby generating a second plurality of signals such that each signal of the second plurality of signals has a first frequency; and

a second circuitry, implemented using C³MOS logic with inductive broadbanding, wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals that correspond to at least one signal of the second plurality of signals, and wherein first and second series connected RL circuits respectively couple first and second output nodes of a logic element to a power supply node, that is operable to;

receive the second plurality of signals; and

process the second plurality of signals thereby generating at least one output signal that has a second frequency.

15. The MOSFET circuit of claim 14, wherein:

the at least one output signal is a serialized signal generated from the second plurality of signals; and

the second frequency is higher than the first frequency.

16. The MOSFET circuit of claim 14, wherein:

the at least one output signal is a serialized signal generated from the second plurality of signals; and

the at least one output signal is launched into a communication channel to which the MOSFET circuit is communicatively coupled.

17. The MOSFET circuit of claim 14, wherein:

first and second capacitive loads respectively coupled to the first and second output nodes of the logic element.

18. The MOSFET circuit of claim 14, wherein:

each RL circuit of the first and second series connected RL circuits includes a resistor and an inductor connected in series; and

the inductor of each RL circuit of the first and second series connected RL circuits is a spiral inductor coupled to the silicon substrate.

19. The MOSFET circuit of claim 14, wherein:

each RL circuit of the first and second series connected RL circuits includes a resistor and an inductor connected in series; and

the resistor of each RL circuit of the first and second series connected RL circuits is a p-channel MOSFET that operates substantially in its linear operating region.

20. The MOSFET circuit of claim 14, wherein:

each signal of the first plurality of signals has a third frequency;

the third frequency is lower than the first frequency; and

the second frequency is higher than the first frequency.