Semiconductor integrated circuit having built-in PLL circuit

• US 7,015,735 B2
• Filed: 12/19/2003
• Issued: 03/21/2006
• Est. Priority Date: 12/19/2003
• Status: Active Grant

• Current Assignee: Epoch Microelectronics, Inc., Renesas Electronics Corporation
• Original Assignee: Epoch Microelectronics, Inc., Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Shimizu, Satoshi, Kimura, Yasuyuki, Dec, Aleksander, Suyama, Ken, Yokota, Masakatsu
• Primary Examiner(s): Nguyen, Minh
• Application Number:
  US10/739,117
• Publication Number:
  US 20050134391A1
• Time in Patent Office: 823 Days
• Field of Search: 327/147, 327/148, 327/156, 327/157, 327/162, 327538-543, 375373-376, 331 15- 17, 331/14, 331/DIG.2
• US Class Current: 327/157
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence

Abstract

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Claims

1. A semiconductor integrated circuit having a built-in PLL circuit, said PLL circuit including:

a voltage controlled oscillator circuit;

a phase comparator circuit for comparing an oscillating signal generated by said voltage controlled oscillator circuit with a reference signal in phase to generate a first signal and a second signal in accordance with a difference in phase between the oscillating signal and the reference signal;

a charge pump circuit configured to operate in response to the first signal and the second signal generated by said phase comparator circuit;

a loop filter having capacitive elements charged and discharged by said charge pump circuits; and

a voltage regulator including a bipolar transistor for generating a base-emitter voltage as a reference for a predetermined voltage generated by said voltage regulator, a first resistive element connected in series with said bipolar transistor, a series connection of a second resistive element and a switching element connected in parallel with said first resistive element, and a temperature detector circuit for detecting a temperature to generate an output for controlling said switching element to switch the voltage generated by said voltage regulator in accordance with the detected temperature, wherein said voltage controlled oscillator circuit is configured to operate with the predetermined voltage generated by said voltage regulator.

2. A semiconductor integrated circuit having a built-in PLL circuit according to claim 1, wherein said voltage regulator comprises a plurality of sets of the series connection of said second resistive element and said switching element connected in parallel with said first resistive element.

3. A semiconductor integrated circuit having a built-in PLL circuit according to claim 1, wherein said voltage regulator further comprises a circuit having a hysteresis characteristic for communicating the output of said temperature detector circuit to a control terminal of said switching element.

4. A semiconductor integrated circuit having a built-in PLL circuit according to claim 1, wherein said voltage regulator further comprises a latch circuit for latching the output of said temperature detector circuit.

5. A semiconductor integrated circuit having a built-in PLL circuit according to claim 1, wherein said temperature detector circuit includes a switching element capable of shutting off an internal current path, and said temperature detector circuit is made inoperative when said switching element shuts off the current path.

6. A semiconductor integrated circuit having a built-in PLL circuit, said PLL circuit including:

a voltage controlled oscillator circuit;

a phase comparator circuit for comparing an oscillating signal generated by said voltage controlled oscillator circuit with a reference signal in phase to generate a first signal and a second signal in accordance with a difference in phase between the oscillating signal and the reference signal;

a first charge pump circuit and a second charge pump circuit configured to operate in response to the first signal and the second signal generated by said phase comparator circuit, each of said first and second charge pump circuits including a charging current source and a discharging current source, wherein said current sources included in said second charge pump circuit generate currents, the absolute values of which are smaller than the absolute values of currents generated by said current sources included in said first charge pump circuit;

said charging current source of said first charge pump circuit and said discharging current source of said second charge pump circuit being controlled by said first signal, and said discharging current source of said first charge pump circuit and said charging current source of said second charge pump circuit being controlled by said second signal;

a loop filter including a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element, wherein said first capacitive element is charged and discharged by said first charge pump circuit, and said second capacitive element is charged and discharged by said second charge pump circuit; and

a voltage regulator including a bipolar transistor for generating a base-emitter voltage as a reference for a predetermined voltage generated by said voltage regulator, a first resistive element connected in series with said bipolar transistor, a series connection of a second resistive element and a switching element connected in parallel with said first resistive element, and a temperature detector circuit for detecting a temperature to generate an output for controlling said switching element to switch the voltage generated by said voltage regulator in accordance with the detected temperature, wherein said first and second charge pump circuit are configured to operate with the predetermined voltage generated by said voltage regulator.

7. A semiconductor integrated circuit according to claim 6, wherein said reference signal is a phase-modulated signal, and said PLL circuit is a transmission PLL circuit for upconverting a transmission signal.