Adaptive body bias for clock skew compensation

• US 7,015,741 B2
• Filed: 12/23/2003
• Issued: 03/21/2006
• Est. Priority Date: 12/23/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Narendra, Siva G., Tschanz, James W., De, Vivek K., Barkatullah, Javed, Kurd, Nasser
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US10/745,029
• Publication Number:
  US 20050134361A1
• Time in Patent Office: 819 Days
• Field of Search: 327534-535, 327291-293, 327/295, 327/158
• US Class Current: 327/295
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 5/1506 with parallel driven output stages; with synchronously driven series connected output stages

Abstract

Transistor bodies are biased to modify delay in clock buffers.

Claims

1. An apparatus comprising:

a bias voltage distribution network comprising a central bias generator to produce at least one reference voltage, and a plurality of local bias generators to receive the at least one reference voltage and produce a plurality of bias voltages;

a plurality of clock buffers having transistor bodies coupled to receive the plurality of bias voltages from the bias voltage distribution network; and

at least one comparison circuit coupled between the plurality of clock buffers and the bias voltage distribution network, wherein the at least one comparison circuit comprises a phase detector to measure a phase difference between signals driven by at least two of the plurality of clock buffers, and to provide an error signal to the bias voltage distribution network;

wherein both the central bias generator and the at least one local bias generator are coupled to receive the error signal.

2. The apparatus of claim 1 wherein the plurality of clock buffers are divided into a plurality of clock networks.

3. The apparatus of claim 2 wherein the plurality of local bias generators comprises a multiplexer.

4. The apparatus of claim 2 wherein the plurality of local bias generators comprises one local bias generator for each clock network.

5. The apparatus of claim 1 wherein the plurality of clock buffers include complementary transistors coupled to upper and lower power supply nodes.

6. The apparatus of claim 5 wherein the central bias generator includes a circuit to produce a reference voltage between an upper power supply voltage on the upper power supply node and a lower power supply voltage on the lower power supply node.

7. The apparatus of claim 5 wherein the central bias generator includes a circuit to produce a reference voltage above an upper power supply voltage on the upper power supply node.

8. The apparatus of claim 5 wherein the central bias generator includes a circuit to produce a reference voltage below a lower power supply voltage on the lower power supply node.

9. An electronic system comprising:

an antenna;

a radio frequency circuit coupled to the antenna; and

a digital circuit coupled to the radio frequency circuit, the digital circuit including variable delay clock buffers, a central bias generator to produce at least one reference voltage, and a local bias generator to receive the at least one reference voltage and produce a bias voltage, the local bias generator being coupled to the variable delay clock buffers, and a comparison circuit to produce an error signal from a comparison of two signals from the variable delay clock buffers, wherein the central bias generator and local bias generator are both coupled to receive the error signal.

10. The electronic system of claim 9 wherein the variable delay clock buffers are formed into a plurality of clock networks having clock delay values set by the bias voltage.

11. The electronic system of claim 9 wherein the variable delay clock buffers include transistor bodies coupled to receive the bias voltage.

12. The electronic system of claim 9 further comprising a plurality of local bias generators.

13. The electronic system of claim 9 wherein the comparison circuit comprises a phase detector.

14. A method comprising:

generating a plurality of bias voltages at a central bias generator;

selecting one of the plurality of bias voltages at a local bias generator to produce a selected bias voltage;

applying the selected bias voltage to a body of a transistor in a clock buffer;

measuring a delay of the clock buffer to produce an error signal;

modifying the plurality of bias voltages in response to the error signal; and

selecting a different one of the plurality of bias voltages in response to the error signal.

15. The method of claim 14 further comprising applying a second bias voltage to a second clock buffer.

16. The method of claim 15 wherein measuring a delay comprises comparing phases of signals driven by the clock buffer and the second clock buffer.

17. An apparatus comprising:

clock buffers with variable delay influenced by body bias;

a bias voltage generation network including a central bias generator to produce at least one reference voltage, and a local bias generator to receive the at least one reference voltage and to influence the delay of the clock buffers; and

an error signal generation circuit to produce an error signal in response to the variable delay in the clock buffers, wherein the central bias generator and local bias generator are coupled to be responsive to an error signal from the error signal generation circuit.

18. The apparatus of claim 17 wherein the clock buffers are arranged to form a plurality of clock networks.

19. The apparatus of claim 18 wherein the error signal generation circuit comprises a phase detector to compare clock signals from at least two of the plurality of clock networks.

20. The apparatus of claim 17 wherein the central bias generator is coupled to produce a plurality of reference voltages in response to the error signal.

21. An apparatus comprising:

clock buffers with variable delay influenced by body bias;

a bias voltage generation network including a central bias generator and a local bias generator; and

an error signal generation circuit to produce an error signal in response to the variable delay in the clock buffers, wherein the central bias generator and local bias generator are coupled to be responsive to an error signal from the error signal generation circuit;

wherein the central bias generator is coupled to produce a plurality of reference voltages in response to the error signal and wherein the local bias generator is coupled to select one of the plurality of bias voltages in response to the error signal.

22. The apparatus of claim 21 wherein the clock buffers are arranged to form a plurality of clock networks.

23. The apparatus of claim 22 wherein the error signal generation circuit comprises a phase detector to compare clock signals from at least two of the plurality of clock networks.