Adaptive predistortion for a transmit system with gain, phase and delay adjustments

• US 7,015,752 B2
• Filed: 08/13/2003
• Issued: 03/21/2006
• Est. Priority Date: 07/03/2003
• Status: Expired due to Term

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Icefyre Semiconductor Incorporated
• Inventors: Saed, Aryan
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US10/641,374
• Publication Number:
  US 20050001679A1
• Time in Patent Office: 951 Days
• Field of Search: 330/149, 330/107, 330/136, 330/280, 330/124.R
• US Class Current: 330/149
• CPC Class Codes: H03F 1/0294 using vector summing of two or more constant amplitude phase-modulated signals
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2201/3233 Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 3/24 of transmitter output stages

Abstract

Systems and methods relating to the provision of gain, phase and delay adjustments to signals to be used by a predistortion subsystem. A portion of an input signal is delayed by delay elements prior to being received by the predistortion subsystem. The delayed input signal portion is also received by a feedback signal processing subsystem that adjusts the gain and phase of the feedback signal based on the delayed input signal portion. The adjusted feedback signal is used, along with the delayed portion of the input signal, to determine an appropriate predistortion modification to be applied to the input signal.

Claims

1. A system for processing an input signal, the system comprising:

an adaptive predistortion subsystem for receiving said input signal and for producing a predistorted signal by applying a deliberate predistortion to said input signal;

a signal processing subsystem receiving and processing said predistorted signal and producing a system output signal;

a feedback signal processing subsystem for receiving and processing a feedback signal derived from said system output signal; and

a delay subsystem for providing a delay to a replica of said input signal to produce a delayed signal, said delayed signal being used by said adaptive predistortion subsystem and said feedback processing subsystem, wherein

said adaptive predistortion subsystem distorts said input signal to compensate for distortions in said system output signal;

said signal processing subsystem decomposes said predistorted signal into separate components, each of said separate components being processed separately;

said processing subsystem combines said components after processing to produce said system output signal;

an output of said feedback processing subsystem being used by said adaptive predistortion subsystem;

said deliberate predistortion applied to said input signal by said adaptive predistortion subsystem to produce said predistorted signal is adjusted based on said system output signal.

2. A system according to claim 1 wherein said signal processing subsystem comprises:

a signal decomposer for decomposing said predistorted signal into at least two components;

at least two signal component processor blocks, each signal processor block receiving an output of said signal decomposer and each signal processor block separately processes said output received from said signal decomposer; and

a combiner receiving a processed output from each of said at least two signal component processor blocks, said combiner producing said system output signal from said processed outputs of said at least two signal component processor blocks.

3. A system according to claim 2 wherein at least one of said at least two signal component processor blocks includes an amplifier.

4. A system according to claim 3 wherein said amplifier is a non-linear amplifier.

5. A system according to claim 1 wherein said system is part of a signal transmission system.

6. A system according to claim 1 wherein at least some of said distortions are due to said combiner.

7. A system according to claim 3 wherein said amplifier is a switch mode amplifier.

8. A system according to claim 3 wherein said amplifier has a low output impedance.

9. A system according to claim 1 wherein said deliberate predistortion includes magnitude distortions which adjust a magnitude of said input signal.

10. A system according to claim 1 wherein said deliberate predistortion includes phase distortions which adjust a phase of said input signal.

11. A system according to claim 1 wherein said deliberate predistortion is based on at least one entry in a lookup table.

12. A system according to claim 1 wherein said predistortion subsystem receives a replica of said system output signal.

13. A system according to claim 2 wherein said deliberate predistortion is dependent on differences between said input signal and said replica of said system output signal.

14. A system according to claim 11 wherein entries in said lookup table are periodically updated based on characteristics of a replica of said system output signal.

15. A system according to claim 11 wherein said deliberate predistortion is based on an interpolation of entries in said table.

16. A system according to claim 1 wherein said predistortion subsystem includes:

determining means for determining said deliberate predistortion;

adjustment means for applying said deliberate predistortion to said input signal;

update means for periodically updating said determining means based on said system output signal.

17. A system according to claim 16 wherein said adjustment means receives parameters of said deliberate predistortion from said determining means.

18. A system according to claim 1 wherein said delay subsystem comprises:

a plurality of delay elements;

means for sampling said input signal;

means for storing samples of said input signal;

means for selecting selected samples of said input signal; and

means for combining said selected samples of said input signal.

19. A system according to claim 1 wherein said delay subsystem comprises separate subsystems for separately delaying a magnitude and a phase of said input signal.

20. A system according to claim 1 wherein said feedback signal processing subsystem comprises means for adjusting a phase of a replica of said system output signal.

21. A system according to claim 1 wherein said predistorted signal is adjusted based on said system output signal and said input signal.

22. A system according to claim 16 wherein said update means periodically updates said determining means based on said system output signal and said input signal.