Device and method for SPR detection in a Mode-S transponder

• US 7,015,856 B1
• Filed: 06/14/2004
• Issued: 03/21/2006
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: Garmin International, Inc. (Garmin Limited)
• Original Assignee: Garmin International, Inc. (Garmin Limited)
• Inventors: Johnson, Timothy L.
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US10/866,925
• Time in Patent Office: 645 Days
• Field of Search: 244 31- 33, 342 29- 51, 342/175, 342/195, 375/340, 375/354, 375/355, 375/358, 375359-370, 375/256, 375/238, 375/316
• US Class Current: 342/32
• CPC Class Codes: G01S 13/782 using multimoding or selective addressing

Abstract

A Mode-S transponder is provided for detecting synchronization phase reversal (SPR) signals. The transponder includes a receiver for receiving a Mode-S signal that contains a P6 pulse having a Mode-S data segment and an SPR signal therein. The transponder also includes a phase detector that detects a phase change between first and second states in the received Mode-S signal. The phase detector includes an SPR qualifier that determine whether, following a state change, the Mode-S signal remains at one of the first and second states for at least a predetermined minimum time sufficient to qualify as a detector enable signal.

Claims

1. In a Mode-S transponder, a subsystem for detecting synchronization signals, comprising:

a receiver for receiving a transponder signal containing at least a first pulse containing a transponder data segment having an synchronization signal; and

a phase detector for detecting a state change between first and second states, said state change corresponding to a change in phase of said transponder signal, said phase detector including a qualifier for determining whether, following said state change, said transponder signal remains at one of said first and second states for at least a predetermined minimum time.

2. The transponder subsystem of claim 1, wherein said qualifier further comprises a series of state latches latching states of said transponder signal at consecutive clock cycles along said transponder signal to identify a length of time at which said transponder signal remains at one of said first and second states.

3. The transponder subsystem of claim 1, wherein said qualifier further comprises logic gates determining whether said transponder signal includes a predefined number of consecutive clock cycles having a common one of said first and second states, said logic gates generating a detector enable signal enabling said phase detector when said first pulse has said common one of said first and second states for said predefined number of consecutive clock cycles.

4. The transponder subsystem of claim 1, wherein said qualifier qualifies said transponder data segment when said transponder data segment includes a detector enable signal maintaining a constant state for at least 50 nsec.

5. The transponder subsystem of claim 1, wherein said qualifier qualifies said transponder data segment when said transponder data segment includes a detector enable signal maintaining a constant state for at least 100 nsec.

6. The transponder subsystem of claim 1, wherein said transponder signal also contains a second pulse that is asynchronous with respect to said synchronization signal.

7. The transponder subsystem of claim 1, said phase detector further comprising a delay line connected to an output of said qualifier, and a comparator comparing states of said transponder signal during previous and current clock cycles.

8. The transponder subsystem of claim 1, further comprising a detector determining whether said detector enable signal determined by said qualifier constitutes a valid signal.

9. The transponder subsystem of claim 1, further comprising a detector determining whether said detector enable signal determined by said qualifier falls within an acceptance window following a leading edge of said first pulse.

10. The transponder subsystem of claim 1, further comprising a delay counter counting down a predetermined time delay following a leading edge of said first signal before enabling said qualifier.

11. The transponder subsystem of claim 1, further comprising a window timer for counting down a length of an acceptance time window during which said transponder signal must occur to be a valid transponder signal.

12. A Mode-S transponder, comprising:

a receiver for receiving air traffic communications signals from an Air Traffic Control Radar Beacon System (ATCRBS);

a demodulator for demodulating said air traffic communications signals and outputting a data segment formatted in accordance with a predefined mode of communications; and

a detection module for validating a synchronization pulse embedded within said data segment based in part upon a length of said synchronization pulse.

13. The transponder of claim 12, wherein said processor determines whether an amplitude of said air traffic communication signals is greater than a threshold.

14. The transponder of claim 12, wherein said predefined mode of communications constitutes Mode-S and said synchronization pulse constitutes an SPR signal in a P6 data pulse of a Mode-S signal.

15. The transponder of claim 12, wherein said detection module includes an SPR qualifier determining whether a state change in said synchronization pulse is maintained for at least a predetermined minimum length of time sufficient to qualify said synchronization pulse as a detector enable signal.

16. A subsystem for controlling reply of a transponder to Mode-S interrogation signals, comprising:

an input for receiving Mode-S signals containing a reference pulse and a P6 pulse, each of said P6 pulses containing a sink phase reversal (SPR) signal followed by a data segment containing Mode-S data, said reference and P6 pulses being separated in time by a pulse separation time and differing in amplitude from one another by a pulse amplitude difference;

means for comparing at least one of said pulse amplitude difference and said pulse separation time with an amplitude difference threshold and a separation time threshold, respectively;

means for setting at least one of said amplitude difference threshold and said separation time threshold such that said SPR signal is correctly identified in at least 95% of said received Mode-S signals in which said amplitude of said P6 pulse is at least 12 dB greater than said amplitude of said reference pulse; and

an output for producing a reply to Mode-S signals for which said SPR signal is correctly identified.

17. The subsystem of claim 16, wherein said means for setting sets said at least one of said amplitude difference threshold and said separation time threshold such that said SPR signal Is identified correctly in at least 97% of said received Mode-S signals in which said amplitude of said P6 pulse is at least 6 dB greater than said amplitude of said reference pulse.

18. The subsystem of claim 16, wherein said means for setting sets said at least one of said amplitude difference threshold and said separation time threshold such that said SPR signal is correctly identified in at least 55% of said received Mode-S signals in which said amplitude of said P6 pulse is at least 3 dB greater than said amplitude of said reference pulse.

19. The subsystem of claim 16, further comprising means for determining whether said P6 pulse changes state within an SPR acceptance window of time following a leading edge of said P6 pulse, thereby qualifying as a potential SPR signal.

20. The subsystem of claim 16, further comprising means for determining whether said P6 pulse changes state from a first state to a second state and remains at said second state for at least a minimum time period, sufficient to qualify as a potential SPR signal.