MEMS devices monolithically integrated with drive and control circuitry

• US 7,015,885 B2
• Filed: 06/04/2004
• Issued: 03/21/2006
• Est. Priority Date: 03/22/2003
• Status: Expired due to Term

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Active Optical Networks, Inc.
• Inventors: Novotny, Vlad, Sastri, Bharat, Reddy, Chitranjan N.
• Primary Examiner(s): Epps, Georgia
• Assistant Examiner(s): Dinh, Jack
• Application Number:
  US10/861,963
• Publication Number:
  US 20050002079A1
• Time in Patent Office: 655 Days
• Field of Search: 345/84, 345/87, 345/89, 345/204
• US Class Current: 345/84
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

Described are MEMS mirror arrays monolithically integrated with CMOS control electronics. The MEMS arrays include polysilicon or polysilicon-germanium components that are mechanically superior to metals used in other MEMS applications, but that require process temperatures not compatible with conventional CMOS technologies. CMOS circuits used with the polysilicon or polysilicon-germanium MEMS structures use interconnect materials that can withstand the high temperatures used during MEMS fabrication. These interconnect materials include doped polysilicon, polycides, and tungsten metal.

Claims

1. A memory array comprising:

a. a plurality of bitlines;

b. a plurality of wordlines;

c. an array of transistors, each transistor including a first current-carrying terminal coupled to one of the bitlines, a second current-carrying terminal, and a control terminal coupled to one of the wordlines; and

d. an array of variable capacitors, each variable capacitor including a first capacitor electrode, coupled to a respective one of the second current-carrying terminals of the array of transistors, and a second capacitor electrode, wherein each of the variable capacitors exhibits a first capacitance with a first voltage applied between the first and second capacitor electrodes and a second capacitance with a second voltage applied between the first and second capacitor electrodes.

5. The memory array of claim 1, wherein the first and second capacitor electrodes include a plurality of comb teeth.

2. The memory array of claim 2, each capacitor further comprising a hinge.

3. The memory array of claim 2, wherein the hinge comprises a semiconductor.

4. The memory array of claim 3, wherein the semiconductor is highly doped.