Single transistor non-volatile memory system, design, and operation
First Claim
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1. A memory system comprising:
- a read bitline;
a plurality of memory cells, each of the plurality of memory cells having conductive and non-conductive states, each memory cell including;
a programming dielectric having first and second dielectric terminals;
a memory transistor having a first current-carrying terminal directly connected to the read bitline, a second current-carrying terminal, and a control terminal connected to the first dielectric terminal; and
a capacitor having a first capacitor terminal, connected to the control terminal of the memory transistor, and a second capacitor terminal; and
wherein the memory cells are arranged in a column of memory cells, the memory system further including a configuration bitline interconnecting the second dielectric terminals.
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Abstract
Described are area-efficient non-volatile memory systems. Non-volatile memory cells in these systems include only one transistor, two fewer than conventional non-volatile memory cells, and reduced interconnect. The simplicity of the memory cells reduces memory-system area, improves manufacturing yield, and consequently reduces cost. New program, erase, and read methodologies have been developed for use with the simplified memory cells.
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17 Claims
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1. A memory system comprising:
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a read bitline; a plurality of memory cells, each of the plurality of memory cells having conductive and non-conductive states, each memory cell including; a programming dielectric having first and second dielectric terminals; a memory transistor having a first current-carrying terminal directly connected to the read bitline, a second current-carrying terminal, and a control terminal connected to the first dielectric terminal; and a capacitor having a first capacitor terminal, connected to the control terminal of the memory transistor, and a second capacitor terminal; and wherein the memory cells are arranged in a column of memory cells, the memory system further including a configuration bitline interconnecting the second dielectric terminals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of configuring a first of a plurality of memory cells in a memory column, the memory column including a configuration bitline connected to each of the memory cells, a read bitline connected to each of the memory cells, and a plurality of control-gate lines, one of the control lines for each of the memory cells, the method comprising:
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applying a first programming voltage to the configuration bitline; applying a second programming voltage to the control-gate line connected to the first of the plurality of memory cells; and applying a program-inhibit voltage to the control-gate line of a second of the plurality of memory cells. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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Specification