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Single transistor non-volatile memory system, design, and operation

  • US 7,016,219 B1
  • Filed: 12/16/2003
  • Issued: 03/21/2006
  • Est. Priority Date: 12/16/2003
  • Status: Active Grant
First Claim
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1. A memory system comprising:

  • a read bitline;

    a plurality of memory cells, each of the plurality of memory cells having conductive and non-conductive states, each memory cell including;

    a programming dielectric having first and second dielectric terminals;

    a memory transistor having a first current-carrying terminal directly connected to the read bitline, a second current-carrying terminal, and a control terminal connected to the first dielectric terminal; and

    a capacitor having a first capacitor terminal, connected to the control terminal of the memory transistor, and a second capacitor terminal; and

    wherein the memory cells are arranged in a column of memory cells, the memory system further including a configuration bitline interconnecting the second dielectric terminals.

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