Synchronization state detector

• US 7,016,448 B2
• Filed: 03/29/2001
• Issued: 03/21/2006
• Est. Priority Date: 03/29/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Boerstler, David William
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US09/820,512
• Publication Number:
  US 20020172312A1
• Time in Patent Office: 1,818 Days
• Field of Search: 375/326, 375/327, 375/371, 375/373, 375/376, 370/516, 370/518, 327/144, 327/146, 327/147
• US Class Current: 375/373
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A system and method for reducing timing uncertainties in a serial data signal A system may comprise a transmitter configured to transmit serial data to a receiver through a transmission medium, e.g., wireless, wired. The receiver may comprise an oscillator configured to generate multiple phases of a clock. The receiver may further comprise a retiming mechanism configured to reduce the timing uncertainties of the serial data received by the receiver by selecting a particular phase of the clock to be asserted to sample the serial data signal. The particular phase may be selected by selecting the appropriate synchronization state/retiming state. A retiming state indicates which particular phase of the clock should be asserted to sample the serial data signal. A synchronization state indicates which particular phase of the clock is the appropriate one to assert at a given transition of the serial data signal.

Claims

1. A receiver comprising:

an input configured to receive serial data;

an oscillator configured to generate phases of a clock; and

a retiming mechanism configured to receive said serial data and said phases of said clock, wherein said retiming mechanism includes circuitry for reducing timing uncertainties in said serial data by selecting a particular phase of said clock to be asserted to sample said serial data during a period of said serial data, wherein each particular phase of said clock to be asserted to sample said serial data during said period of said serial data corresponds to a particular retiming state, wherein each particular retiming state is paired with a particular synchronization state, wherein said particular synchronization state indicates which particular phase of said clock to assert at a given transition of said serial data.

2. The receiver as recited in claim 1, wherein said retiming mechanism comprises a first unit, wherein said first unit includes circuitry for generating logical values of each particular synchronization state/retiming state pair.

3. The receiver as recited in claim 2, wherein said first unit receives said phases of said clock and said serial data.

4. The receiver as recited in claim 3, wherein said first unit comprises a sample clock mechanism configured to sample values of said phases of said clock.

5. The receiver as recited in claim 4, wherein said first unit comprises a plurality of second units, wherein said sampled phase values are inputted to said plurality of second units, wherein said plurality of second units includes circuitry for generating said logical values of each particular synchronization state/retiming state pair.

6. The receiver as recited in claim 5, wherein said plurality of second units outputs said logical values of each particular synchronization state/retiming state pair to a completion detector, wherein said completion detector includes circuitry for generating a signal indicating a time to sample inputs of said completion detector.

7. The receiver as recited in claim 6, wherein said first unit comprises a third unit configured to detect one of said inputs of said completion detector that has not changed state upon said completion detector generating said signal, wherein said one of said inputs that did not change state corresponds to a particular synchronization state/retiming state pair to be asserted.

8. The receiver as recited in claim 5, wherein each of said plurality of second units comprises circuitry for performing a NOR function on particular sampled phase values.

9. The receiver as recited in claim 6, wherein said completion detector comprises circuitry for performing a NOR function on said logical values of each particular synchronization state/retiming state pair outputted by said plurality of second units.

10. The receiver as recited in claim 1, wherein said oscillator operates at a frequency lower than a data rate of said serial data.

11. A system comprising:

a transmission medium;

a transmitter coupled to said transmission medium, wherein said transmitter is configured to transmit data in a serial form; and

a receiver coupled to said transmission medium, wherein said receiver is configured to receive said serial data, wherein said receiver comprises an oscillator configured to generate phases of a clock, wherein said receiver further comprises a retiming mechanism configured to receive said serial data and said phases of said clock, wherein said retiming mechanism includes circuitry for reducing timing uncertainties in said serial data by selecting a particular chase of said clock to be asserted to sample said serial data during a period of said serial data;

wherein each particular chase of said clock to be asserted to sample said serial data during said period of said serial data corresponds to a particular retiming state;

wherein each particular retiming state is paired with a particular synchronization state, wherein said particular synchronization state indicates which particular phase of said clock to assert at a given transition of said serial data.

12. The system as recited in claim 11, wherein said retiming mechanism comprises a first unit, wherein said first unit includes circuitry for generating logical values of each particular synchronization state/retiming state pair.

13. The system as recited in claim 12, wherein said first unit receives said phases of said clock and said serial data.

14. The system as recited in claim 13, wherein said first unit comprises a sample clock mechanism configured to sample values of said phases of said clock.

15. The system as recited in claim 14, wherein said first unit comprises a plurality of second units, wherein said sampled phase values are inputted to said plurality of second units, wherein said plurality of second units includes circuitry for generating said logical values of each particular synchronization state/retiming state pair.

16. The system as recited in claim 15, wherein said plurality of second units outputs said logical values of each particular synchronization state/retiming state pair to a completion detector, wherein said completion detector includes circuitry for generating a signal indicating a time to sample inputs of said completion detector.

17. The system as recited in claim 16, wherein said first unit comprises a third unit configured to detect one of said inputs of said completion detector that has not changed state upon said completion detector generating said signal, wherein said one of said inputs that did not change state corresponds to a particular synchronization state/retiming state pair to be asserted.

18. The system as recited in claim 15, wherein each of said plurality of second units comprises circuitry for performing a NOR function on particular sampled phase values.

19. The system as recited in claim 16, wherein said completion detector comprises circuitry for performing a NOR function on said logical values of each particular synchronization state/retiming state pair outputted by said plurality of second units.

20. The system as recited in claim 11, wherein said oscillator operates at a frequency lower than a data rate of said serial data.