Timing recovery and frequency tracking system and method

• US 7,016,449 B2
• Filed: 04/30/2001
• Issued: 03/21/2006
• Est. Priority Date: 04/28/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wakayama, Myles, Wang, Hui, Baumer, Howard A., Jiang, Xicheng, Le, Michael, Buchwald, Aaron W., Van Engelen, Jurgen, Madisetti, Avanindra
• Primary Examiner(s): Fan, Chieh M.
• Assistant Examiner(s): Perilla, Jason M.
• Application Number:
  US09/844,432
• Publication Number:
  US 20020039395A1
• Time in Patent Office: 1,786 Days
• Field of Search: 375/355, 375/362, 375/371, 375/373, 375/376, 375/316, 375/327, 375/354, 375/356, 375/357, 375/375
• US Class Current: 375/373
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0274 with Costas loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Claims

1. A system for recovering timing information from a serial data signal, comprising:

a phase interpolator adapted to derive a data sampling signal and a phase sampling signal each having an interpolated phase responsive to a plurality of phase control signals, wherein the phase sampling signal is offset in phase relative to the data sampling signal by a predetermined amount;

a data path adapted to sample the serial data signal according to the data sampling signal to produce a data signal;

a phase path adapted to sample the serial data signal according to the phase sampling signal to produce a phase signal;

a phase detector adapted to produce a phase error signal based on the data signal and the phase signal, wherein the phase error signal is indicative of a phase offset between the data sampling signal and the serial data signal;

a phase error processor coupled to the phase detector and adapted to produce a frequency offset estimate signal based on long-term error processing of the phase error signal, wherein the frequency offset estimate signal is indicative of a frequency offset between the data sampling signal and the serial data signal;

a command generator coupled to the phase error processor and adapted to generate a rotator control signal in response to the frequency offset estimate signal; and

a control signal rotator adapted to manipulate the plurality of phase control signals in response to the rotator control signal, whereby the control signal rotator is adapted to cause the phase interpolator to rotate the interpolated phase of the data sampling signal and the phase sampling signal.

2. The system of claim 1, wherein the control signal rotator is adapted to cause the phase interpolator to rotate the interpolated phase of the data sampling signal and phase sampling signal at a rate corresponding to the frequency offset so as to reduce the frequency offset between the data sampling signal and the serial data signal.

3. The system of claim 1, wherein the control signal rotator causes the phase interpolator to repetitively rotate the interpolated phase of the data sampling signal and the phase sampling signal through a range of phases spanning 360°

at a rate corresponding to the frequency offset.

4. The system of claim 3, wherein the control signal rotator is adapted to cause the phase interpolator to:

rotate the interpolated phase of the data sampling signal and the phase sampling signal in a direction of increasing phase to decrease a frequency of the data sampling signal and the phase sampling signal when the frequency offset estimate signal indicates the frequency of the data sampling signal is greater than a frequency of the serial data signal; and

rotate the interpolated phase of the data sampling signal and the phase sampling signal in a direction of decreasing phase to increase the frequency of the data sampling signal and the phase sampling signal when the frequency offset estimate signal indicates the frequency of the data sampling signal is less than the frequency of the serial data signal.

5. The system of claim 1, wherein the phase interpolator comprises:

a plurality of reference stages adapted to control individual magnitudes of a plurality of component signals having different phases responsive to the plurality of phase control signals; and

a combining node adapted to combine the plurality of component signals into the interpolated data sampling signal.

6. The system of claim 1, wherein the control signal rotator is adapted to apply the plurality of phase control signals to the phase interpolator to control the interpolated phase of the data sampling signal and the phase sampling signal, based on the rotator control signal.

7. The system of claim 6, wherein the control signal rotator is adapted to rotate the plurality of phase control signals, and correspondingly, the interpolated phase of the data sampling signal and the phase sampling signal according to the rotator control signal.

8. The system of claim 1, wherein the control signal rotator is adapted to apply the plurality of phase control signals to the phase interpolator to control the interpolated phase of the data sampling signal and the phase sampling signal, the control signal rotator being adapted to rotate the plurality of phase control signals, and correspondingly the interpolated phase of the data sampling signal and the phase sampling signal, at a rate corresponding to the frequency offset, responsive to the rotator control signal.

9. The system of claim 8, wherein the rotator control signal is one of a phase-advance, a phase-retard, and a phase-hold signal, the control signal rotator being adapted to:

rotate the plurality of phase control signals in a first direction to advance the interpolated phase of the data timing signal and the phase sampling signal in response to the phase-advance signal;

rotate the plurality of phase control signals in a second direction to retard the interpolated phase of the data timing signal and the phase sampling signal in response to the phase-retard signal; and

prevent the plurality of phase control signals and correspondingly the interpolated phase of the data timing signal and the phase sampling signal from rotating in response to the phase-hold signal.

19. The system of claim 1, wherein the phase error processor comprises a long-term error processor, wherein the long-term error processor integrates the phase error signal over a relatively long time period to cause the frequency offset estimate signal to respond slowly to changes in the phase offset between the data sampling signal and the serial data signal.

20. The system of claim 19, wherein the long-term error processor comprises an accumulator.

21. The system of claim 1, wherein the phase sampling signal is offset in phase relative to the data sampling signal by a predetermined amount corresponding to a fraction of a symbol period of the serial data signal.

22. The system of claim 21, wherein the phase sampling signal is offset in phase relative to the data sampling signal by one-half of a symbol period of the serial data signal.

10. A method of recovering timing information from a serial data signal, comprising:

(a) deriving a data sampling signal and a phase sampling signal each having an interpolated phase, wherein the phase sampling signal is offset in phase relative to the data sampling signal by a predetermined amount;

(b) sampling the serial data signal according to the data sampling signal to produce a data signal;

(c) sampling the serial data signal according to the phase sampling signal to produce a phase signal;

(d) producing a phase error signal based on the data signal and phase signal, wherein the phase error signal is indicative of a phase offset between the data sampling signal and the serial data signal;

(e) estimating a frequency offset between the data sampling signal and the serial data signal based on long-term processing of the phase error signal; and

(f) rotating the interpolated phase of the data sampling signal and the phase sampling signal to reduce the frequency offset between the data sampling signal and the serial data signal.

11. The method of claim 10, wherein step (f) further comprises rotating the interpolated phase of the data sampling signal and the phase sampling signal at a rate corresponding to the frequency offset.

12. The method of claim 10, wherein step (f) further comprises repetitively rotating the interpolated phase of the data sampling signal and phase sampling signal through a range of phases spanning 360°

at a rate corresponding to the frequency offset.

13. The method of claim 12, wherein step (f) further comprises:

rotating the interpolated phase of the data sampling signal and phase sampling signal in a direction of increasing phase to decrease a frequency of the data sampling signal and phase sampling signal when the frequency of the data sampling signal is greater than a frequency of the serial data signal; and

rotating the interpolated phase of the data sampling signal and phase sampling signal in a direction of decreasing phase to increase the frequency of the data sampling signal and phase sampling signal when the frequency of the data sampling signal is less than the frequency of the serial data signal.

14. The method of claim 10, wherein step (a) further comprises deriving the interpolated phase of the data sampling signal and the phase sampling signal responsive to a plurality of phase control signals, the method further comprising manipulating the plurality of phase control signals responsive to the frequency offset.

15. The method of claim 14, wherein step (f) further comprises rotating the plurality of phase control signals, and correspondingly, the interpolated phase of the data sampling signal and phase sampling signal according to the frequency offset.

16. The method of claim 10, wherein step (e) further comprises deriving a frequency error signal based on the frequency offset and step (f) further comprises rotating the interpolated phase of the data sampling signal and the phase sampling signal according to the frequency error signal.

17. The method of claim 10, wherein step (a) further comprises:

controlling individual magnitudes of a plurality of component signals having different phases responsive to a plurality of phase control signals; and

combining the plurality of component signals into the data sampling signal having the interpolated phase.

18. The method of claim 10, wherein step (f) comprises synchronizing a frequency of the data sampling signal to a frequency of the serial data signal.

23. The method of claim 10, wherein the long-term error processing of step (e) further comprises integrating the phase error signal over a relatively long time period to cause an estimate of the frequency offset to respond slowly to changes in the phase offset between the data sampling signal and the received serial data signal.

24. The method of claim 23, further comprising implementing the long-term error processing with an accumulator.

25. The method of claim 10, wherein step (a) further comprises offsetting the phase sampling signal in phase relative to the data sampling signal by a predetermined amount corresponding to a fraction of a symbol period of the serial data signal.

26. The method of claim 25, wherein step (a) further comprises offsetting the phase sampling signal in phase relative to the data sampling signal by one-half of a symbol period of the serial data signal.