Reversible embedded wavelet system implementation
First Claim
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1. A system comprising:
- a buffer;
a wavelet transform unit having an input coupled to the buffer to perform a reversible wavelet transform on pixels stored in the buffer and to generate coefficients at an output;
a coder coupled to the wavelet transform unit to code bitplanes of wavelet transformed pixels from the wavelet transform unit and stored bitplanes of wavelet transformed pixels received from the buffer, wherein the coder comprisesa context model, anda parallel entropy coder encoder, andwherein the most important data is not embedded and is coded in coefficient order without buffering, a portion of less important data is buffered, embedded and written to memory in order of importance.
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Abstract
A method and apparatus for performing compression and/or decompression is described. In one embodiment, the present invention comprises a system having a buffer, a wavelet transform unit, and a coder. The wavelet transform unit has an input coupled to the buffer to perform a wavelet transform on pixels stored therein and to generate coefficients at an output. The coder is coupled to the wavelet transform unit to code the transformed pixels received from the buffer.
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Citations
25 Claims
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1. A system comprising:
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a buffer; a wavelet transform unit having an input coupled to the buffer to perform a reversible wavelet transform on pixels stored in the buffer and to generate coefficients at an output; a coder coupled to the wavelet transform unit to code bitplanes of wavelet transformed pixels from the wavelet transform unit and stored bitplanes of wavelet transformed pixels received from the buffer, wherein the coder comprises a context model, and a parallel entropy coder encoder, and wherein the most important data is not embedded and is coded in coefficient order without buffering, a portion of less important data is buffered, embedded and written to memory in order of importance. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit (IC) chip comprising:
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a pixel data interface to transfer pixel data between the IC chip and memory; a reversible wavelet transform coupled to the pixel data interface to transfer information to and from the memory via the pixel data interface; a context model coupled to the reversible wavelet transform to provide contexts for coding the data provided therefrom; and an encoder to encode coefficients generated by the reversible wavelet transform based on contexts provided by the context model, wherein the encoder encodes a first data of coefficients in a set of coefficients in coefficient order, and wherein the encoder then encodes a second data and embeds the second data by order based, in part, on a plurality of signaling bits, the first data having a higher priority than the second data. - View Dependent Claims (8, 9, 10, 11, 12, 13, 24)
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14. A system comprising:
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a context model; a probability estimation machine coupled to the context model; a bit generator coupled to the probability estimation machine; and an encoder rate control coupled to an output of the bit generator to control the encoding rate by determining average codeword length, wherein the encoder rate control encodes a first data of coefficients in a coefficient order, and wherein the encoder rate control then encodes a second data and embeds the second data by order based, in part, on a plurality of signaling bits, the first data having a higher priority than the second data. - View Dependent Claims (15, 16, 17, 18)
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19. A system comprising:
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modeling means for providing contexts; probability estimating means for providing probability estimates in response to contexts from the context model; bit generation means for providing zero or more bits in response to probability estimates from the probability estimating means; and encoder rate control means for coupled to an output of the bit generation means for controlling the encoding rate by determining average codeword length, wherein the encoder rate control means encodes a first data of coefficients in a coefficient order, and wherein the encoder rate control means then encodes a second data and embeds the second data by order based on at least one or more signaling bits, the first data having a higher importance than the second data. - View Dependent Claims (20, 21, 22, 23)
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25. An integrated circuit (IC) chip comprising:
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a pixel data interface to transfer pixel data between the IC chip and memory; a reversible wavelet transform coupled to the pixel data interface to transfer information to and from the memory via the pixel data interface; a context model coupled to the reversible wavelet transform to provide contexts for coding the data provided therefrom; and an encoder to encode coefficients generated by the reversible wavelet transform based on contexts provided by the context model, wherein the encoder codes the most important data of coefficients in a set of coefficients immediately in coefficient order and then codes the less important data and embeds the less important data by order based, in part, on a plurality of signaling bits.
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Specification