Programmable power-efficient front end for wired and wireless communication

• US 7,016,654 B1
• Filed: 04/30/2002
• Issued: 03/21/2006
• Est. Priority Date: 04/30/2001
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Engim, Inc.
• Inventors: Bugeja, Alex
• Primary Examiner(s): Trinh, Sonny
• Assistant Examiner(s): DOAN, PHUOC HUU
• Application Number:
  US10/135,776
• Time in Patent Office: 1,421 Days
• Field of Search: 455/20, 455/574, 455/522, 455/127.1, 455/73, 455/550.1, 455/552, 455/343.1, 455/343.2, 370/320, 370/336, 370/347
• US Class Current: 455/73
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04B 1/18 Input circuits, e.g. for coupling to an antenna or a transmission line coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H
• CPC Class Codes: H04B 2001/045 with means for improving efficiency

Abstract

A front-end used for processing communication signals in a received path including an antenna cable segment that receives the communication signals. A RF segment provides mixing and filtering of the received signals, the RF segment outputs a first set of signals. An analog baseband segment performs low pass filtering and digitizes the first set of signals in order to input a second set of signals for further processing. The RF segment and the analog baseband segment includes a selective set of components that are power programmable, such that the power consumption of the selective set of components are controlled by bias currents delivered to each of the selective components. In another embodiment, the components of a transmit path are also power programmable via bias current. In another embodiment, the ADCs and DACs of a receive and transmit paths are power programmable via bias current and reconfigurable blocks of ADC and DAC cores.

Claims

1. A front-end used for processing communication signals in a received path, comprising:

an antenna cable segment that receives said communication signals;

a RF segment that provides mixing and filtering of said received signals, said RF segment outputting a first set of signals; and

an analog baseband segment that performs low pass filtering and digitizes said first set of signals in order to input a second set of signals for further processing, said analog baseband segment comprising at least one analog to digital converter core;

wherein

said RF segment and said analog baseband segment includes a selective set of components that are power programmable, such that the power consumption of said selective set of components is scaled commensurate with bandwidth being utilized and controlled by bias current delivered to each of said selective components;

said at least one analog to digital converter core includes a reconfigurable block including one or more of said analog to digital converter cores, wherein each of said one or more analog to digital converter cores receiving an analog input signal and outputting a digitize signal, each of said one or more analog to digital converter cores also include a plurality of stages for performing analog to digital conversion;

said reconfigurable block being configured to switch off and on a selective number of said stages to manage the power consumption of said one or more analog to digital converter cores.

2. The front-end as recited in claim 1, wherein said RF segment includes at least one mixer.

3. The front-end as recited in claim 2, wherein said at least one mixer is power programmable, such that the power consumption of said at least one mixer power is controlled by bias currents.

4. The front-end as recited in claim 1, wherein said RF segment includes a low noise amplifier.

5. The front-end as recited in claim 4, wherein said low noise amplifier is power programmable, such that the power consumption of said low noise amplifier power is controlled by bias currents.

6. The front-end as recited in claim 1, wherein said at least one analog to digital converter is power programmable, such that the power consumption of said at least one analog to digital converter is controlled by bias currents.

7. The front-end as recited in claim 1, wherein said analog baseband segment includes at least one low pass filter.

8. The front-end as recited in claim 7, wherein said at least one low pass filter is power programmable, such that the power consumption of said at least one low pass filter is controlled by bias currents.

11. The front-end as recited in claim 1, said at least one digital to analog converter is power programmable, such that the power consumption of said at least one digital to analog converter is controlled by bias currents.

20. The front-end of claim 1, wherein said one or more analog to digital converter cores are switched off selectively at the coarsest level.

21. The front-end of claim 1, wherein said one or more analog to digital converter cores are based on a switched capacitor pipeline implementation.

22. The front-end of claim 1 further comprising a sample and hold device providing input signals to said reconfigurable block.

23. The front-end of claim 22 further comprising a bypass circuit to drive said analog to digital converter.

24. The front-end of claim 1, wherein said one or more analog to digital converter cores include stages for performing the analog to digital conversion.

25. The front-end of claim 1, wherein said one or more analog to digital converter cores are interleaved.

9. A front-end used for processing communication signals in a transmit path, comprising:

an analog baseband that receives modulated signals and performs digital to analog conversion and low pass filtering of said modulated signals, said analog baseband outputting a first set of signals and comprising at least one analog to digital converter core;

an RF segment that performs mixing and power amplification of said first set of signals, said RF outputting a second set of signals; and

an antenna cable segment that organizes said second set of signals for transmission;

wherein

said RF segment and said analog baseband segment includes a selective set of components that are power programmable, such that the power consumption of said selective set of is scaled commensurate with bandwidth being utilized utilized and controlled by bias current delivered to each of said selective components;

said at least one analog to digital converter core includes a reconfigurable block including one or more of said analog to digital converter cores, wherein each of said one or more analog to digital converter cores receiving an analog input signal and outputting a digitize signal, each of said one or more analog to digital converter cores also include a plurality of stages for performing analog to digital conversion;

said reconfigurable block being configured to switch off and on a selective number of said stages to manage the power consumption of said one or more analog to digital converter cores.

10. The front-end as recited in claim 9, wherein power consumption of said selective set of components is controlled by bias current delivered to each of said selective components.

12. The front-end as recited in claim 10, wherein said analog baseband segment includes at least one low pass filter.

13. The front-end as recited in claim 12, wherein said at least one low pass filter is power programmable, such that the power consumption of said at least one low pass filter is controlled by bias currents.

14. The front-end as recited in claim 10, wherein said RF segment includes at least one mixer.

15. The front-end as recited in claim 14, wherein said at least one mixer is power programmable, such that the power consumption of said at least one mixer is controlled by bias currents.

16. The front-end as recited in claim 10, wherein said RF segment includes a pre-amplifier.

17. The front-end as recited in claim 15, said pre-amplifier is power programmable, such that the power consumption of said pre-amplifier is controlled by bias currents.

18. The front-end as recited in claim 10, wherein said RF segment includes a power amplifier.

19. The front-end as recited in claim 18, said power amplifier is power programmable, such that the power consumption of said power amplifier power consumptions is controlled by bias currents.

26. The front-end of claim 9, wherein said one or more digital to analog cores is switched off selectively at the coarsest level.

27. The front-end of claim 9, wherein said digital to analog converter cores are based on a switched capacitor pipeline implementation.

28. The front-end of claim 9 further comprising an amplifier block filtering an processing signals received from said digital to analog converter.

29. The front-end of claim 9, wherein said one or more digital to analog converter cores are interleaved.

30. The front-end of claim 9 further comprising a high amplifier block receiving the output of said one or more digital to analog converter cores and providing dynamic maximum linearity.