System and method for controlling a communication bus

• US 7,016,983 B2
• Filed: 04/12/2003
• Issued: 03/21/2006
• Est. Priority Date: 04/12/2003
• Status: Expired due to Fees

• Current Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Zeng, Qinggang, Li, Weibin
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): SORRELL, ERON J
• Application Number:
  US10/411,716
• Publication Number:
  US 20040215833A1
• Time in Patent Office: 1,074 Days
• Field of Search: 710 62- 68, 386109-112
• US Class Current: 710/5
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A method for controlling communication. The method sends a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus, sends a control signal from the first processor to a selector, the selector switching electrical communication at least one signal line of the processor bus from the first bus to a second bus, sends a second instruction from the first processor to a second device, sends a control signal from the first processor to the selector, the selector switching electrical communication of the at least one signal line of the processor bus from the second bus to the first bus, and sends data from the first device to the first processor. In another aspect, the first processor may transmit the control signal to the selector after comparing a threshold value with a status signal indicating an amount of data stored in the buffer connected to the second processor, the status signal sent from the second processor to the first processor via a status bus.

Claims

1. A system for controlling communication, comprising:

a first processor connected to a selector via a processor bus and a control bus;

the selector placing one or more signal lines of the processor bus in electrical communication with one or more signal lines of one of a first bus and a second bus, the selector responsive to a control signal sent from the first processor via the control bus;

a first device connected to the first bus for accessing a storage medium in response to a first instruction from the first processor;

a second processor connected to the second bus, the second processor having an input for receiving data and attached to a buffer for storing data; and

a second device connected to the second bus, which retrieves and stores the data from the buffer in response to a second instruction from the first processor;

wherein the first processor is configured to issue the first instruction to the first device via the first bus causing the first device to access the storage medium, wherein while the first device is performing according to the first instruction, the first processor transmits the control signal to the selector to select the second bus, and the first processor issues the second instruction to the second device via the second bus causing the second device to retrieve and store the data from the buffer, and wherein after the second device completes performance in accordance to the second instruction, the first processor transmits the control signal to the selector to select the first bus to communicate with the first device relating to the first instruction.

2. The system of claim 1, wherein the first processor transmits the control signal to the selector to select the second bus after comparing a threshold value with a status signal indicating an amount of data stored in the buffer connected to the second processor, the status signal sent from the second processor to the first processor via a status bus.

3. The method of claim 2, wherein the threshold value is selected from a group of one or more threshold values based on an encoding rate.

4. The system of claim 1, wherein the first processor transmits the control signal to the selector to select the second bus in response to a signal sent from the second device.

5. The system of claim 1, wherein the processor bus, the first bus and the second bus are Advanced Technology Attachment-2 (ATA-2) busses.

6. The system of claim 1, wherein the first device is an optical disk drive.

7. The system of claim 1, wherein the second device is a hard disk drive.

8. The system of claim 1, wherein the selector is a field programmable gate array.

9. The system of claim 1, wherein the second processor is an encoder processor.

10. The system of claim 1, wherein the data is audio/video data.

11. A method for controlling communication, comprising:

a) sending a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus;

b) while the first device is performing according to the first instruction, sending a control signal from the first processor to a selector, the selector switching electrical communication of at least one signal line of the processor bus from the first bus to a second bus;

c) sending a second instruction from the first processor to a second device via the second bus;

d) after the second device completes performance in accordance to the second instruction, sending a control signal from the first processor to the selector, the selector switching electrical communication of the at least one signal line of the processor bus from the second bus to the first bus; and

e) sending data from the first device to the first processor to complete the first instruction.

12. The method of claim 11, wherein steps b) through d) are performed after comparing a threshold value with a status signal indicating an amount of data stored in a buffer connected to a second processor, the status signal sent from the second processor to the first processor via a status bus.

13. The method of claim 12, wherein the threshold value is selected from a group of one or more threshold values based on an encoding rate.

14. The method of claim 11, wherein the first instruction is a request to retrieve audio/video data from the first device, and the data sent from the first device is the requested audio/video data.

15. The method of claim 11, wherein the second instruction is a request for the second device to retrieve and store audio/video data from a buffer.

16. The method of claim 11, wherein the processor bus, the first bus and the second bus are Advanced Technology Attachment-2 (ATA-2) busses.

17. The method of claim 11, wherein the first device is an optical disk drive.

18. The method of claim 11, wherein the second device is a hard disk drive.

19. The method of claim 11, wherein the second processor is an encoder processor.

20. The method of claim 11, wherein the selector is a field programmable gate array.

21. A system for controlling communication, comprising:

a first processor connected to a selector via a processor bus and a control bus;

the selector connected to a first bus and a second bus, the selector in one of a first position, a second position, and a third position based on a control signal sent from the first processor via the control bus;

a first device connected to the first bus and configured to receive a first instruction from the first processor;

a second processor connected to the second bus; and

a second device connected to the second bus and configured to receive a second instruction from the first processor;

wherein the first processor is configured to issue the first instruction to the first device via the first bus causing the first device to perform a task, wherein while the first device is performing the task according to the first instruction, the first processor transmits the control signal to the selector to select the second bus, and the first processor issues the second instruction to the second device via the second bus causing the second device to perform a second task, and wherein after the second device completes the second task in accordance to the second instruction, the first processor transmits the control signal to the selector to select the first bus to communicate with the first device relating to the first instruction.

22. The system of claim 21, wherein,

the first position includes one or more signal lines of the processor bus in electrical communication with one or more signal lines of the first bus,

the second position includes one or more signal lines of the processor bus in electrical communication with one or more signal lines of the second bus, and the third position includes one or more signal lines of the processor bus in electrical communication with one or more signal lines, of the first bus.