System featuring a master device, a buffer device and a plurality of integrated circuit memory devices
First Claim
1. A method of operation in a memory system, wherein the memory system includes a master device coupled to a first buffer device, a second buffer device coupled to the first buffer device, a first plurality of memory devices coupled to the first buffer device, and a second plurality of memory devices coupled to the second buffer device, the method comprising:
- the first buffer device transmitting data in the form of unidirectional differential signals to the master device over signal lines of a first plurality of signal lines;
the master device transmitting data, control information and address information in the form of unidirectional differential signals to the first buffer device over signal lines of the first plurality of signal lines; and
transferring data between the first buffer device and the second buffer device using a second plurality of signal lines.
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Abstract
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
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Citations
37 Claims
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1. A method of operation in a memory system, wherein the memory system includes a master device coupled to a first buffer device, a second buffer device coupled to the first buffer device, a first plurality of memory devices coupled to the first buffer device, and a second plurality of memory devices coupled to the second buffer device, the method comprising:
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the first buffer device transmitting data in the form of unidirectional differential signals to the master device over signal lines of a first plurality of signal lines; the master device transmitting data, control information and address information in the form of unidirectional differential signals to the first buffer device over signal lines of the first plurality of signal lines; and transferring data between the first buffer device and the second buffer device using a second plurality of signal lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of operation in a memory system, wherein the memory system includes a master device coupled to a first buffer device and a second buffer device, a first plurality of memory devices coupled to the first buffer device, and a second plurality of memory devices coupled to the second buffer device, the method comprising:
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transmitting data, from the first buffer device to the master device, using unidirectional differential signals on signal lines in a first plurality of signal lines; transmitting data, control information and address information, from the master device to the first buffer device, using unidirectional differential signals on signal lines in the first plurality of signal lines; transmitting data, from a second buffer device to the master device, using unidirectional differential signals on signal lines in a second plurality of signal lines; and transmitting data, control information and address information, from the master device to the second buffer device, using unidirectional differential signals on signal lines in the second plurality of signal lines. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A method comprising:
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disposing a master device on a first substrate; disposing a first connector on the first substrate, the first connector to receive a first memory module that includes a first buffer device coupled to a first plurality of memory devices, such that when the first memory module is received by the first connector, the first plurality of memory devices are accessed by the master device using unidirectional differential signaling between the master device and the first buffer device; disposing a second connector on the first substrate, the second connector to receive a second memory module that includes a second buffer device coupled to a first plurality of memory devices, such that when the second memory module is received by the second connector, the second plurality of memory devices are accessed by the master device using unidirectional differential signaling between the master device and the second buffer device. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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36. A method of operation in a memory system, wherein the memory system includes a master device, a first integrated circuit buffer device on a first memory module having a first plurality of integrated circuit memory devices, a second integrated circuit buffer device on a second memory module having a second plurality of integrated circuit memory devices, a third integrated circuit buffer device on a third memory module having a third plurality of integrated circuit memory devices, and a fourth integrated circuit buffer device on a fourth memory module having a fourth plurality of integrated circuit memory devices, the method comprising:
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step for communicating between the master device and the first integrated circuit buffer device; step for communicating between the master device and the second integrated circuit buffer device; step for communicating between the first buffer device and the third integrated circuit buffer device; and step for communicating between the third integrated circuit buffer device and the fourth integrated circuit buffer device.
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37. A method of operation in a memory system, wherein the memory system includes a master device, a first integrated circuit buffer device on a first memory module having a first plurality of integrated circuit memory devices, and a second integrated circuit buffer device on a second memory module having a second plurality of integrated circuit memory devices, comprising:
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step for communicating between the master device and the first integrated circuit buffer device; and step for communicating between the master device and the second integrated circuit buffer device.
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Specification