System featuring a master device, a buffer device and a plurality of integrated circuit memory devices

• US 7,017,002 B2
• Filed: 09/28/2004
• Issued: 03/21/2006
• Est. Priority Date: 01/05/2000
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Sidiropoulos, Stefanos, Tsern, Ely
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US10/952,610
• Publication Number:
  US 20050041504A1
• Time in Patent Office: 539 Days
• Field of Search: None
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.

Claims

1. A method of operation in a memory system, wherein the memory system includes a master device coupled to a first buffer device, a second buffer device coupled to the first buffer device, a first plurality of memory devices coupled to the first buffer device, and a second plurality of memory devices coupled to the second buffer device, the method comprising:

the first buffer device transmitting data in the form of unidirectional differential signals to the master device over signal lines of a first plurality of signal lines;

the master device transmitting data, control information and address information in the form of unidirectional differential signals to the first buffer device over signal lines of the first plurality of signal lines; and

transferring data between the first buffer device and the second buffer device using a second plurality of signal lines.

2. The method of claim 1, wherein the transferring includes communicating data in the form of unidirectional differential signals from the first buffer device to the second buffer device over signal lines in the second plurality of signal lines, and communicating data in the form of unidirectional differential signals from the second buffer device to the first buffer device over signal lines in the second plurality of signal lines.

3. The method of claim 2, further comprising transceiving, by the first buffer device, signals between the first plurality of signal lines and the second plurality of signal lines.

4. The method of claim 1, further comprising providing a first termination disposed on the master device, wherein the first termination is coupled to a signal line of the first plurality of signal lines.

5. The method of claim 4, further comprising providing a second termination disposed on the first buffer device, wherein the second termination is coupled to a signal line of the first plurality of signal lines.

6. The method of claim 1, wherein the first plurality of signal lines are a first plurality of point-to-point links, wherein the first plurality of point-to-point links include a first connection to the master device and a second connection to the first buffer device.

7. The method of claim 1, wherein the master device transmitting includes transmitting, by a transmitter in the master device, data onto a first signal line of the first plurality of signal lines, and further comprising:

receiving, by a receiver in the master device, data from a second signal line of the first plurality of signal lines.

8. The method of claim 7, further comprising:

receiving, by a receiver in the first buffer device coupled to the first signal line, data that is transmitted using the transmitter in the master device; and

wherein the first buffer device transmitting includes transmitting, by a transmitter in the first buffer device coupled to the second signal line, data that is received by the receiver in the master device.

9. The method of claim 1, further comprising:

disposing the master device and the first plurality of signal lines on a first substrate including a first connector coupled to the first plurality of signal lines;

disposing the first buffer device and the first plurality of integrated circuit memory devices on a second substrate; and

coupling the second substrate to the first substrate by way of the first connector.

10. The method of claim 9, wherein the first substrate is a motherboard substrate and the second substrate is a memory module substrate.

11. The method of claim 9, further comprising:

disposing the second buffer device and the second plurality of integrated circuit memory devices on a third substrate.

12. The method of claim 1, wherein the master device is a processor device.

13. The method of claim 1, wherein the master device is a controller device.

14. The method of claim 1, wherein the first plurality of integrated circuit memory devices are dynamic random access memories.

15. The method of claim 1, further comprising:

transferring data between a third buffer device, coupled to a third plurality of integrated circuit memory devices, and the second buffer device over a third plurality of signal lines, wherein the first buffer device, the second buffer device, and the third buffer device are coupled together in a daisy chain configuration.

16. The method of claim 1, further comprising:

transferring data between a third buffer device, coupled to a third plurality of integrated circuit memory devices, and the master device over a third plurality of signal lines.

17. The method of claim 16, wherein the first plurality of signal lines form a first plurality of point-to-point links between the master device and the first buffer device, the second plurality of signal lines form a second plurality of point-to-point links between the first buffer device and the second buffer device, and the third plurality of signal lines form a third plurality of point-to-point links between the master device and the third buffer device.

18. The method of claim 1, further comprising:

initializing the first buffer device and the second buffer device using sideband signals.

19. A method of operation in a memory system, wherein the memory system includes a master device coupled to a first buffer device and a second buffer device, a first plurality of memory devices coupled to the first buffer device, and a second plurality of memory devices coupled to the second buffer device, the method comprising:

transmitting data, from the first buffer device to the master device, using unidirectional differential signals on signal lines in a first plurality of signal lines;

transmitting data, control information and address information, from the master device to the first buffer device, using unidirectional differential signals on signal lines in the first plurality of signal lines;

transmitting data, from a second buffer device to the master device, using unidirectional differential signals on signal lines in a second plurality of signal lines; and

transmitting data, control information and address information, from the master device to the second buffer device, using unidirectional differential signals on signal lines in the second plurality of signal lines.

20. The method of claim 19, further comprising:

providing a first plurality of terminators disposed on the master device, to terminate a first end of each signal line of the first plurality of signal lines and the second plurality of signal lines.

21. The method of claim 20, further comprising:

providing a second plurality of terminators disposed on the first buffer device, to terminate a second end of each signal line of the first plurality of signal lines; and

providing a third plurality of terminators disposed on the second buffer device, to terminate a second end of each signal line of the second plurality of signal lines.

22. The method of claim 19, wherein:

the first plurality of signal lines include a first point-to-point link, wherein the first point-to-point link includes a first connection to the master device and a second connection to the first buffer device; and

the second plurality of signal lines include a second point-to-point link, wherein the second point-to-point link includes a first connection to the master device and a second connection to the second buffer device.

23. The method of claim 19, including:

transmitting data, by a first transmitter of the master device, onto a first signal line of the first plurality of signal lines;

receiving data, by a first receiver of the master device, from a second signal line of the first plurality of signal lines;

transmitting data, by a second transmitter of the master device, onto a first signal line of the second plurality of signal lines; and

receiving data, by a second receiver of the master device, from a second signal line of the second plurality of signal lines.

24. The method of claim 23, including:

receiving data, by a receiver of the first buffer device, coupled to the first signal line of the first plurality of signal lines, that is transmitted using the first transmitter of the master device;

transmitting data, by a transmitter of the first buffer device, coupled to the second signal line of the first plurality of signal lines, that is received by the first receiver of the master device;

receiving data, by a receiver of the second buffer device, coupled to the first signal line of the second plurality of signal lines, that is transmitted using the second transmitter of the master device; and

transmitting data, by a transmitter of the second buffer device, coupled to the second signal line of the second plurality of signal lines, that is received by the second receiver of the master device.

25. The method of claim 19, wherein:

disposing the master device, the first plurality of signal lines, and the second plurality of signal lines on a motherboard;

disposing a first socket on the motherboard, the first socket to receive a first memory module that includes the first buffer device and the first plurality of memory devices;

coupling the first socket to the first plurality of signal lines;

disposing a second socket on the motherboard, the second socket to receive a second memory module that includes the second buffer device and the second plurality of memory devices; and

coupling the second socket to the second plurality of signal lines.

26. The method of claim 19, wherein the master device, the first plurality of signal lines and the second plurality of signal lines are disposed on a motherboard, wherein the motherboard includes a first socket coupled to the first plurality of signal lines, and a second socket coupled to the second plurality of signal lines, the method further comprising:

disposing the first plurality of integrated circuit memory devices and the first buffer device on a first memory module, wherein the first memory module includes an edge connector that is insert-able into the first socket; and

disposing the second plurality of integrated circuit memory devices and the second buffer device on a second memory module, wherein the second memory module includes an edge connector that is insert-able into the second socket.

27. The method of claim 19, wherein the first plurality of integrated circuit memory devices are double data rate dynamic random access memories, and the second plurality of integrated circuit memory devices are double data rate dynamic random access memories.

28. The method of claim 19, further comprising:

initializing the first buffer device and the second buffer device using sideband signals on at least one signal line coupled to the first buffer device, the second buffer device and the master device.

29. A method comprising:

disposing a master device on a first substrate;

disposing a first connector on the first substrate, the first connector to receive a first memory module that includes a first buffer device coupled to a first plurality of memory devices, such that when the first memory module is received by the first connector, the first plurality of memory devices are accessed by the master device using unidirectional differential signaling between the master device and the first buffer device;

disposing a second connector on the first substrate, the second connector to receive a second memory module that includes a second buffer device coupled to a first plurality of memory devices, such that when the second memory module is received by the second connector, the second plurality of memory devices are accessed by the master device using unidirectional differential signaling between the master device and the second buffer device.

30. The method of claim 29, wherein when the second memory module is received by the second connector and the first memory module is received by the first connector, the second plurality of memory devices are accessed by the master device using unidirectional differential signaling between the master device and the first buffer device and unidirectional differential signaling between the first buffer device and the second buffer device, wherein the first buffer device and the second buffer device are coupled in a daisy chain configuration.

31. The method of claim 29, further including disposing a first plurality of signal lines on the motherboard, wherein the first plurality of signal lines include a first point to point link, wherein the first point to point link includes a first connection to the master device and a second connection to the first buffer device when the second memory module is received in the second connector.

32. The method of claim 31, further including disposing a second plurality of signal lines on the motherboard, wherein the second plurality of signal lines include first connections to the first buffer device when the first memory module is received in the first connector, and second connections to the second buffer device when the second memory module is received in the second connector.

33. The method of claim 29, wherein the first plurality of integrated circuit memory devices are dynamic random access memories, and the second plurality of integrated circuit memory devices are dynamic random access memories.

34. The method of claim 29, further comprising:

disposing signal lines for sideband signals on the first substrate, such that the sideband signals are used to initialize the first buffer device when the first memory module is received by the first connector and the second memory module is received by the second connector.

35. The method of claim 29, wherein the first substrate is a printed circuit board, the first connector is a socket and the second connector is a socket.

36. A method of operation in a memory system, wherein the memory system includes a master device, a first integrated circuit buffer device on a first memory module having a first plurality of integrated circuit memory devices, a second integrated circuit buffer device on a second memory module having a second plurality of integrated circuit memory devices, a third integrated circuit buffer device on a third memory module having a third plurality of integrated circuit memory devices, and a fourth integrated circuit buffer device on a fourth memory module having a fourth plurality of integrated circuit memory devices, the method comprising:

step for communicating between the master device and the first integrated circuit buffer device;

step for communicating between the master device and the second integrated circuit buffer device;

step for communicating between the first buffer device and the third integrated circuit buffer device; and

step for communicating between the third integrated circuit buffer device and the fourth integrated circuit buffer device.

37. A method of operation in a memory system, wherein the memory system includes a master device, a first integrated circuit buffer device on a first memory module having a first plurality of integrated circuit memory devices, and a second integrated circuit buffer device on a second memory module having a second plurality of integrated circuit memory devices, comprising:

step for communicating between the master device and the first integrated circuit buffer device; and

step for communicating between the master device and the second integrated circuit buffer device.