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System featuring a master device, a buffer device and a plurality of integrated circuit memory devices

  • US 7,017,002 B2
  • Filed: 09/28/2004
  • Issued: 03/21/2006
  • Est. Priority Date: 01/05/2000
  • Status: Expired due to Fees
First Claim
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1. A method of operation in a memory system, wherein the memory system includes a master device coupled to a first buffer device, a second buffer device coupled to the first buffer device, a first plurality of memory devices coupled to the first buffer device, and a second plurality of memory devices coupled to the second buffer device, the method comprising:

  • the first buffer device transmitting data in the form of unidirectional differential signals to the master device over signal lines of a first plurality of signal lines;

    the master device transmitting data, control information and address information in the form of unidirectional differential signals to the first buffer device over signal lines of the first plurality of signal lines; and

    transferring data between the first buffer device and the second buffer device using a second plurality of signal lines.

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