Data processing system having no system memory

• US 7,017,024 B2
• Filed: 12/12/2002
• Issued: 03/21/2006
• Est. Priority Date: 12/12/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ghai, Sanjeev, Arimilli, Ravi Kumar, Wright, Kenneth Lee, Dodson, John Steven
• Primary Examiner(s): PATEL, HETUL B
• Application Number:
  US10/319,023
• Publication Number:
  US 20040117591A1
• Time in Patent Office: 1,195 Days
• Field of Search: 711202-203, 711/206, 711/221, 711/205, 711/207, 711/104, 711111-113
• US Class Current: 711/202
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address.

Claims

1. A data processing system capable of utilizing a virtual memory processing scheme, said data processing system comprising:

a plurality of processing units, wherein said plurality of processing units have volatile cache memoryies operating in a virtual address space;

an interconnect coupled to said plurality of processing units and volatile cache memories;

a non-volatile physical storage device coupled to said plurality of processing units via said interconnect, wherein said virtual address space of said plurality of processing units directly maps to a physical disk address space of said non-volatile physical storage device; and

a storage controller coupled to said interconnect for directly mapping a virtual address from one of said volatile cache memories to a physical disk address directed to a storage location within said non-volatile physical storage device without transitioning through an intermediate translation.

2. The data processing system of claim 1, wherein said non-volatile physical storage device is a hard disk.

3. The data processing system of claim 2, wherein said bard disk is coupled to said interconnect via an input/output channel converter.

4. The data processing system of claim 3, wherein said hard disk is coupled to said input/output channel converter via an adapter.