Built-in self-test for multi-channel transceivers without data alignment

• US 7,017,098 B2
• Filed: 01/23/2004
• Issued: 03/21/2006
• Est. Priority Date: 08/11/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Cao, Jun, Momtaz, Afshin
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US10/764,093
• Publication Number:
  US 20040153931A1
• Time in Patent Office: 788 Days
• Field of Search: 714/715, 714/738, 714/742, 714/729, 714/724, 714/712, 714/733
• US Class Current: 714/742
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: H04B 17/19 Self-testing arrangements
• CPC Class Codes: H04B 17/20 of receivers

Abstract

A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplary embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Claims

1. A circuit for testing a transceiver, comprising:

a test pattern generator generating a first test pattern and a second test pattern;

a multiplexer having a first input, a second input, and an output, the first input receiving the first test pattern and the second input receiving the second test pattern;

a demultiplexer having an input, a first output, and a second output, the input of the demultiplexer being coupled to the output of the multiplexer; and

a test result evaluation circuit generating a first signature based on a first data stream generated by the first output of the demultiplexer and a second signature based on a second data stream generated by the second output of the demultiplexer, the test result evaluation circuit comparing each generated signature to a stored signature for determining whether an error has occurred during the transmission of an associated data stream.

2. The circuit of claim 1, wherein the first test pattern is different from the second test pattern.

3. The circuit of claim 1, wherein the first signature is equal to the second signature.

4. The circuit of claim 1, wherein the test result evaluation circuit further includes:

a controller identifying a start of a particular data stream; and

a recorder recording the data stream in response to the identification.

5. The circuit of claim 4, wherein the start of the particular data stream is identified based on an identification of a specific bit sequence in the data stream.

6. The circuit of claim 4, wherein a particular signature is generated based on the recorded data stream.

7. The circuit of claim 1 further comprising:

a selector coupled to the multiplexer, the selector selecting between an input signal data, and the first and second test patterns generated by the test pattern generator.

8. The circuit of claim 1, wherein the selector selects the first and second test patterns during a testing mode, and the input signal data during a non-testing mode.

9. The circuit of claim 1, wherein the circuit is integrated within the transceiver circuitry.

10. A circuit for testing a transceiver, comprising:

means for generating a first test pattern and a second test pattern;

a multiplexer having a first input, a second input, and an output, the first input receiving the first test pattern and the second input receiving the second test pattern;

a demultiplexer having an input, a first output, and a second output, the input of the demultiplexer being coupled to the output of the multiplexer; and

means for generating a first signature based on a first data stream generated by the first output of the demultiplexer and a second signature based on a second data stream generated by the second output of the demultiplexer;

means for comparing each generated signature to a stored signature; and

means for determining, based on the comparison, whether an error has occurred during the transmission an associated data stream.

11. The circuit of claim 10, wherein the first test pattern is different from the second test pattern.

12. The circuit of claim 10, wherein the first signature is equal to the second signature.

13. The circuit of claim 10 further comprising:

means for identifying a start of a particular data stream; and

means for recording the data stream in response to the identification.

14. The circuit of claim 13, wherein the start of the particular data stream is identified based on an identification of a specific bit sequence in the data stream.

15. The circuit of claim 13, wherein the means for generating a signature generates a particular signature based on the recorded data stream.

16. The circuit of claim 10 further comprising:

means for selecting between an input signal data, and the first and second test patterns generated by the test pattern generator.

17. The circuit of claim 10, wherein the means for selecting selects the first and second test patterns during a testing mode, and the input signal data during a non-testing mode.

18. The circuit of claim 10, wherein the circuit is integrated within the transceiver circuitry.