Method of designing semiconductor integrated circuit utilizing a scan test function

• US 7,017,135 B2
• Filed: 04/30/2001
• Issued: 03/21/2006
• Est. Priority Date: 02/20/1996
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ichinomiya, Takahiro, Takeoka, Sadami, Motohara, Akira
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US09/843,687
• Publication Number:
  US 20010021990A1
• Time in Patent Office: 1,786 Days
• Field of Search: 716/2, 716/4, 716/11, 716/14, 716/6, 716/12
• US Class Current: 716/115
• CPC Class Codes: G01R 31/318586 with partial scan or non-scannable parts

Abstract

A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Claims

1. A method of wiring a semiconductor integrated circuit to include a scan chain between first and second memory elements previously selected in the semiconductor integrated circuit, said method comprising:

an element connecting step of connecting one of plural output terminals of a first memory element with a scan data input terminal of a second memory element having a scan test function,

wherein said element connecting step includes steps of;

calculating a beeline distance on a substrate from each of said output terminals of said first memory element to said scan data input terminal of said second memory element; and

connecting one of said output terminals of said first memory element having a minimum beeline distance to said scan data input terminal of said second memory element with said scan data input terminal of said second memory element.

2. A method of wiring a semiconductor integrated circuit to include a scan chain between first and second memory elements previously selected in the semiconductor integrated circuit, said method comprising:

an element connecting step of connecting one of plural output terminals of a first memory element with a scan data input terminal of a second memory element having a scan test function,

wherein said element connecting step includes steps of;

calculating wire lengths to be laid from said output terminals of said first memory element to said scan data input terminal of said second memory element; and

connecting one of said output terminals of said first memory element having a minimum wire length with said scan data input terminal of said second memory element.

3. A method of wiring a semiconductor integrated circuit to include a scan chain between first and second memory elements previously selected in the semiconductor integrated circuit, said method comprising:

an element connecting step of connecting one of plural output terminals of a first memory element with a scan data input terminal of a second memory element having a scan test function,

wherein said element connecting step includes steps of;

calculating fan-out of said output terminals of said first memory element; and

connecting one of aid output terminals having minimum fan-out with said scan data input terminal of said second memory element.

4. A method of wiring a semiconductor integrated circuit to include a scan chain between first and second memory elements previously selected in the semiconductor integrated circuit, said method comprising:

an element connecting step of connecting one of plural output terminals of a first memory element with a scan data input terminal of a second memory element having a scan test function,

wherein said element connecting step includes steps of;

calculating load capacitances of said output terminals of said first memory element; and

connecting one of said output terminals of said first memory element having a minimum load capacitance with said scan data input terminal of said second memory element.