Insulated-gate field-effect thin film transistors

• US 7,018,875 B2
• Filed: 01/23/2004
• Issued: 03/28/2006
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Viciciv Technology, Inc.
• Inventors: Madurawe, Raminda U.
• Primary Examiner(s): Pham, Long
• Application Number:
  US10/762,627
• Publication Number:
  US 20040152245A1
• Time in Patent Office: 795 Days
• Field of Search: 438/151, 438/197, 438/275
• US Class Current: 438/151
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor Gated-FET device comprises a lightly doped resistive channel region formed on a first semiconductor thin film layer; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.

Claims

1. A method of fabricating a semiconductor Insulated-Gate Field-Effect Transistor (Gated-FET), comprising:

depositing a semiconductor thin film layer on a thick insulator; and

forming a substantially rectangular channel region in said semiconductor thin film layer, said channel region lightly doped to form a resistive channel, wherein the height of the channel region comprising the entire thin film thickness; and

depositing a gate insulator layer above said channel region; and

depositing a gate material above said gate insulator layer, said material forming a gate region above said channel region;

wherein optimizing said thin film properties, gate insulator properties and gate material properties such that said gate region further comprises;

a first voltage level that modulates said channel resistance to a substantially non-conductive state by fully depleting majority carriers from said channel region; and

a second voltage level that modulates said channel resistance to a substantially conductive state by at least partially accumulating majority carriers near the gate insulator surface in said channel region; and

wherein depositing said semiconductor thin film layer further comprises;

defining a surface voltage as Φ

_S=V_D−

V_FB−

T_G*Q_S/∈

_G; and

defining a surface dopant level as N_S=D*exp(qΦ

_S/kT); and

defining a first thickness as L_D=[∈

_S*kT/(q²N_S)]^0.5; and

defining a second thickness as X_A=√

2*L_D*[(N_S/D)^0.5−

1]; and

defining a surface charge as Q_S=q*N_S*X_A/(1+X_A/(√

2*L_D)]; and

iteratively identifying the consistent set of values that satisfies said definitions; and

depositing a substantially uniform thickness T_S of said semiconductor thin film layer, wherein said thickness T_S is greater than said second thickness X_A;

where, V_D is power supply voltage level, ∈

_S is channel semiconductor permittivity, ∈

_G is gate insulator permittivity, T_G is gate insulator thickness, V_FB is gate material to semiconductor channel absolute flat band voltage, k is the Boltzmann'"'"'s constant, T is the absolute temperature, q is electron charge and D is channel region doping level.

2. The method of claim 1, wherein depositing said semiconductor thin film layer further comprises:

defining a third thickness as X=∈

_S*T_G/∈

_G; and

defining a fourth thickness as Y=[(2*∈

_S*(V_FB−

V_T))/(q*D)]^0.5; and

defining a fifth thickness as Z=(X²+Y²)^0.5−

X; and

depositing said substantially uniform thickness T_S of said semiconductor thin film layer, wherein said thickness T_S satisfies a thickness range approximately 0.8*Z to 1.2*Z;

where, ∈

_S is channel semiconductor permittivity, ∈

_G is gate insulator permittivity, T_G is gate insulator thickness, V_FB is gate material to semiconductor channel absolute flat band voltage, V_T is channel region absolute threshold voltage, q is electron charge and D is channel region doping level.

3. The method of claim 1, wherein said gate insulator material comprises an oxide, said gate material comprises a heavily doped poly Silicon material with opposite type dopant to said channel region, and depositing said semiconductor thin film layer further comprises:

defining a third thickness as X=3*T_OX (Angstroms); and

defining a fourth thickness as Y=0.28/√

D (Angstroms); and

defining a fifth thickness as Z=(X²+Y²)^0.5−

X (Angstroms); and

depositing said substantially uniform thickness T_S of said semiconductor thin film layer, wherein said thickness T_S further satisfies a thickness range approximately 0.8*Z to 1.2*Z;

where, T_OX is gate oxide thickness in Angstroms, D is channel doping level in atoms/(Angstroms)³ and T_S is channel semiconductor layer thickness in Angstroms.

4. The method of claim 1, comprised of forming one of N channel or P channel Gated-FET thin film transistor consisting a process sequence comprised of:

depositing one of amorphous or crystalline poly-1 (P1);

performing P1 mask &

etching P1;

applying blanket Gated-NFET V_T N−

implant;

applying Gated-PFET V_T mask &

P−

implant;

depositing Gox;

depositing one of amorphous or crystalline poly-2 (P2);

applying blanket P+ implantation of Gated-NFET Gate;

applying N+ mask &

implanting Gated-PFET Gate;

applying P2 mask &

etching P2;

applying blanket LDN N implant (Gated-NFET LDD);

applying LDP mask &

P implant (Gated-PFET LDD);

depositing a spacer oxide and etching the spacer oxide;

depositing Nickel;

salicidizing the Nickel on exposed P1 and P2;

salicidizing P1 completely;

performing RTA anneal, P1 and P2 re-crystallization and dopant anneal;

depositing ILD oxide &

CMP;

applying C2 mask &

etch;

forming a W plug &

CMP; and

depositing M1.

5. The method of claim 1, comprised of forming one of N channel or P channel thinned down SOI Gated-FET thin film transistor consisting a process sequence comprised of:

forming SOI substrate wafer;

performing Shallow Trench isolation;

Trench Etch, Trench Fill and CMP;

depositing Sacrificial oxide;

applying Periphery PMOS V_T mask &

implant;

applying Periphery NMOS V_T mask &

implant;

applying Gated-FET mask and Silicon etch;

performing Gated-FET blanket V_T N implant;

applying Gated-FET V_T P mask and P implant;

performing Dopant activation and anneal;

performing Sacrificial oxide etch;

depositing Gate oxide/Dual gate oxide option;

depositing Gate poly (GP);

applying Gated-FET N+ mask and N+ implant;

applying Gated-FET P+ mask and P+ implant;

applying GP mask &

etch;

applying LDN mask &

N−

implant;

applying LDP mask &

P−

implant;

depositing Spacer oxide &

spacer etch;

applying Periphery N+ mask and N+ implant;

applying Periphery P+ mask and P+ implant;

depositing Ni;

performing RTA anneal—

Ni salicidation (S/D/G regions &

interconnect);

performing Dopant activation;

performing Unreacted Ni etch;

depositing ILD oxide &

CMP; and

applying contact mask and etch.

6. The method of claim 1, comprising forming a source region and a drain region on opposite sides of said substantially rectangular channel region in said semiconductor thin film layer, further comprised of:

doping said source region to a higher level than said channel region, said dopant type same as said channel region; and

doping said drain region to a higher level than said channel region, said dopant type same as said channel region; and

providing a conducting path from said source region to said drain region through said resistive channel region in the middle, said conducting path comprising the entire thickness of the thin film layer;

wherein the absolute value of said channel region threshold voltage V_T comprises a value in the range from 0.10 to 0.40 times a system power voltage level, and preferably in the range 0.15 to 0.30 times a system power voltage level, and more preferably in the range 0.18 to 0.22 times a system power voltage level.

7. A method of fabricating a semiconductor N channel Gated-FET transistor, comprising:

depositing a semiconductor thin film layer on a thick insulator; and

forming a substantially rectangular channel region in said semiconductor thin film layer, said channel region lightly doped with N type dopant to form a resistive channel, wherein the height of the channel region comprising the entire thin film thickness; and

forming a source region and a drain region on opposite sides of said rectangular channel region in said semiconductor thin film layer, said source and drain regions heavily doped with N type dopant; and

depositing a gate insulator layer above said channel region; and

depositing a heavily P type doped poly-silicon gate material above said gate insulator layer, said gate material forming a gate region above said channel region; and

optimizing said thin film properties, gate insulator properties and gate material properties such that said gate region further comprises;

a first voltage level that modulates said channel resistance to a substantially non-conductive state by fully depleting majority carriers from said channel region, said state disconnecting said source from said drain region; and

a second voltage level that modulates said channel resistance to a substantially conductive state by at least partially accumulating majority carriers near the gate insulator surface of said channel region, said state connecting said source to said drain region;

wherein said first voltage level comprises a voltage in the range from system ground voltage level to a threshold voltage level, wherein;

said thin film channel is fully depleted of majority carriers; and

said source region is decoupled from said drain region for a drain to source differential bias voltage ranging from zero to a system power supply voltage.

8. The method of claim 7, wherein said second voltage level comprises a voltage in the range from said threshold voltage level to a flat band voltage level, wherein:

said thin film channel is not fully depleted, said channel comprising majority carriers; and

said source region is coupled to said drain region for a differential bias voltage ranging from zero to a system power supply voltage.

9. The method of claim 7, wherein said second voltage level comprises a voltage in the range from said flat band voltage level to a system power voltage level, wherein:

said thin film channel majority carrier concentration is substantially enhanced above said channel doping level by an accumulation near the gate insulator surface; and

said source region is coupled to said drain region for a differential bias voltage ranging from zero to a system power supply voltage.

10. A method of fabricating a semiconductor P-channel Gated-FET transistor, comprising:

depositing a semiconductor thin film layer on a thick insulator; and

forming a substantially rectangular channel region in said semiconductor thin film layer, said channel region lightly doped with P type dopant to form a resistive channel, wherein the height of the channel region comprising the entire thin film thickness; and

forming a source region and a drain region on opposite sides of said rectangular channel region in said semiconductor thin film layer, said source and drain regions heavily doped with P type dopant; and

depositing a gate insulator layer above said channel region; and

depositing a heavily N type doped poly-silicon gate material above said gate insulator layer, said gate material forming a gate region above said channel region; and

optimizing said thin film properties, gate insulator properties and gate material properties such that said gate region further comprises;

a first voltage level that modulates said channel resistance to a substantially non-conductive state by fully depleting majority carriers from said channel region, said state disconnecting said source from said drain region; and

a second voltage level that modulates said channel resistance to a substantially conductive state by at least partially accumulating majority carriers near the gate insulator surface of said channel region, said state connecting said source to said drain region;

wherein said first voltage level comprises a voltage in the range from a system power voltage level to a threshold voltage below system power voltage level, wherein;

said thin film channel is fully depleted of majority carriers; and

said source region is decoupled from said drain region for a source to drain differential bias voltage ranging from zero to said system power supply voltage.

11. The method of claim 10, wherein said second voltage level comprises a voltage in the range from a flat band voltage level below system power voltage level to said threshold voltage below system power voltage level, wherein:

said thin film channel is not fully depleted, said channel comprising majority carriers; and

said source region is coupled to said drain region for a differential bias voltage ranging from zero to said system power supply voltage.

12. The method of claim 10, wherein said second voltage level comprises a voltage range from a system ground voltage level to said flat band voltage level below system power voltage level, wherein:

said thin film channel majority carrier concentration is substantially enhanced above said channel doping level by an accumulation near the gate insulator surface; and

said source region is coupled to said drain region for a differential bias voltage ranging from zero to said system power supply voltage.