Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions

• US 7,018,900 B2
• Filed: 09/14/2004
• Issued: 03/28/2006
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: RJ Mears LLC (Atomera Incorporated)
• Inventors: Kreps, Scott A.
• Primary Examiner(s): Pham, Long
• Application Number:
  US10/940,418
• Publication Number:
  US 20050090048A1
• Time in Patent Office: 560 Days
• Field of Search: 438/197, 438/285
• US Class Current: 438/285
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may be formed by forming a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The method may further include forming a gate overlying the superlattice channel, and forming source and drain regions in the semiconductor substrate on opposing sides of the superlattice channel so that the superlattice channel has upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions.

Claims

1. A method for making a semiconductor device comprising:

providing a semiconductor substrate; and

forming at least one metal oxide semiconductor field-effect transistor (MOSFET) by

forming a superlattice channel comprising a plurality of stacked groups of layers on the semiconductor substrate, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, and the energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor,

forming a gate overlying the superlattice channel, and

forming source and drain regions in the semiconductor substrate on opposing sides of the superlattice channel so that the superlattice channel has upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions.

2. The method of claim 1 wherein forming the at least one MOSFET further comprises forming an underlying portion of the substrate aligned with the superlattice channel.

3. The method of claim 1 wherein forming the gate comprises forming a gate oxide layer overlying the superlattice channel and a gate electrode thereover;

and wherein the superlattice channel is aligned with the gate electrode.

4. The method of claim 1 wherein forming the gate comprises a gate oxide layer overlying the superlattice channel, a gate electrode thereover, and sidewall spacers on opposing sides of the gate electrode;

and wherein the superlattice channel is aligned with the sidewall spacers.

5. The method of claim 1 wherein the at least one MOSFET comprises a plurality thereof;

and further comprising forming an isolation region in the semiconductor substrate between adjacent MOSFETs.

6. The method of claim 1 further comprising forming a contact layer on at least one of the source and drain regions.

7. The method of claim 1 wherein the superlattice channel has a common energy band structure therein.

8. The method of claim 1 wherein the superlattice channel has a higher charge carrier mobility than would otherwise be present without the non-semiconductor layer.

9. The method of claim 1 wherein each base semiconductor portion comprises silicon.

10. The method of claim 1 wherein each base semiconductor portion comprises germanium.

11. The method of claim 1 wherein each energy band-modifying layer comprises oxygen.

12. The method of claim 1 wherein each energy band-modifying layer is a single monolayer thick.

13. The method of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

14. The method of claim 1 wherein the superlattice further has a substantially direct energy bandgap.

15. The method of claim 1 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

16. The method of claim 1 wherein all of the base semiconductor portions are a same number of monolayers thick.

17. The method of claim 1 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

18. The method of claim 1 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

19. A method for making a semiconductor device comprising:

providing a semiconductor substrate; and

forming at least one metal oxide semiconductor field-effect transistor (MOSFET) by

forming a superlattice channel comprising a plurality of stacked groups of layers on the semiconductor substrate, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, and the energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor,

forming a gate comprising a gate oxide layer overlying the superlattice channel and a gate electrode thereover, the superlattice channel being aligned with the gate electrode,

forming an underlying portion of the substrate aligned with the superlattice channel, and

forming source and drain regions in the semiconductor substrate on opposing sides of the superlattice channel so that the superlattice channel has upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions.

20. The method of claim 19 wherein the at least one MOSFET comprises a plurality thereof;

and further comprising forming an isolation region in the semiconductor substrate between adjacent MOSFETs.

21. The method of claim 19 further comprising forming a contact layer on at least one of the source and drain regions.

22. The method of claim 19 wherein the superlattice channel has a common energy band structure therein.

23. The method of claim 19 wherein the superlattice channel has a higher charge carrier mobility than would otherwise be present without the non-semiconductor layer.

24. The method of claim 19 wherein each base semiconductor portion comprises silicon.

25. The method of claim 19 wherein each base semiconductor portion comprises germanium.

26. The method of claim 19 wherein each energy band-modifying layer comprises oxygen.

27. The method of claim 19 wherein each energy band-modifying layer is a single monolayer thick.

28. The method of claim 19 wherein each base semiconductor portion is less than eight monolayers thick.

29. The method of claim 19 wherein the superlattice further has a substantially direct energy bandgap.

30. The method of claim 19 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

31. The method of claim 19 wherein all of the base semiconductor portions are a same number of monolayers thick.

32. The method of claim 19 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

33. The method of claim 19 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

34. A method for making a semiconductor device comprising:

providing a semiconductor substrate; and

forming at least one metal oxide semiconductor field-effect transistor (MOSFET) by

forming a superlattice channel comprising a plurality of stacked groups of layers on the semiconductor substrate, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, and the energy-band modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor,

forming a gate comprising a gate oxide layer overlying the superlattice channel, a gate electrode thereover, and sidewall spacers on opposing sides of the gate electrode, the superlattice channel being aligned with the sidewall spacers, and

forming an underlying portion of the substrate aligned with the superlattice channel, and

forming source and drain regions in the semiconductor substrate on opposing sides of the superlattice channel so that the superlattice channel has upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions.

35. The method of claim 34 wherein the at least one MOSFET comprises a plurality thereof;

and further comprising forming an isolation region in the semiconductor substrate between adjacent MOSFETs.

36. The method of claim 34 further comprising forming a contact layer on at least one of the source and drain regions.

37. The method of claim 34 wherein the superlattice channel has a common energy band structure therein.

38. The method of claim 34 wherein the superlattice channel has a higher charge carrier mobility than would otherwise be present without the non-semiconductor layer.

39. The method of claim 34 wherein each base semiconductor portion comprises silicon.

40. The method of claim 34 wherein each base semiconductor portion comprises germanium.

41. The method of claim 34 wherein each energy band-modifying layer comprises oxygen.

42. The method of claim 34 wherein each energy band-modifying layer is a single monolayer thick.

43. The method of claim 34 wherein each base semiconductor portion is less than eight monolayers thick.

44. The method of claim 34 wherein the superlattice further has a substantially direct energy bandgap.

45. The method of claim 34 wherein the superlattice further comprises a base semiconductor cap layer on an uppermost group of layers.

46. The method of claim 34 wherein all of the base semiconductor portions are a same number of monolayers thick.

47. The method of claim 34 wherein at least some of the base semiconductor portions are a different number of monolayers thick.

48. The method of claim 34 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.