High voltage level translator

• US 7,019,560 B2
• Filed: 01/13/2003
• Issued: 03/28/2006
• Est. Priority Date: 01/13/2003
• Status: Expired due to Fees

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Knierim, David L., Wimmer, Guenther W.
• Primary Examiner(s): Chang, Daniel D.
• Application Number:
  US10/263,512
• Publication Number:
  US 20040136130A1
• Time in Patent Office: 1,170 Days
• Field of Search: 326 95- 98, 326/63, 326/68, 326/83, 327/113, 327/333, 327/108, 327/110
• US Class Current: 326/96
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/0455 Details of switching sections of circuit, e.g. transistors
• CPC Class Codes: B41J 2/04581 controlling heads based on piezoelectric elements

Abstract

A circuit for controlling a piezoelectric transducer includes an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp is a positive going pulse train, and a source electrode coupled to an output Vcntrl for controlling the transducer and a charging circuit, responsive to a low voltage input signal Vpp_sel, for charging the FET gate to a bias voltage greater than the FET'"'"'s threshold voltage while Vpp is near zero volts and for maintaining the bias voltage on the FET gate while Vpp ramps up to a value greater than the bias voltage and until Vpp_sel is removed. The control circuit reduces switching time and reduces current spikes in the power supplies to the chip.

Claims

1. A circuit for controlling a capacitive load, comprising:

an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp comprises a positive going pulse train, and a source electrode coupled to an output Vcntrl for controlling the load; and

a charging circuit, responsive to a low voltage input signal Vpp_sel, for charging the FET gate to a bias voltage greater than the FET gate'"'"'s threshold voltage while Vpp is near zero volts and for maintaining the bias voltage on the FET gate while Vpp ramps up to a value greater than the bias voltage and until Vpp_sel is removed.

2. The circuit of claim 1, wherein the capacitance of the N-channel FET gate maintains the bias voltage on the gate until Vpp_sel is removed.

3. The circuit of claim 1, further comprising:

a charge removal circuit, responsive to removal of Vpp_sel, for removing the charge on the FET gate such that no substantial DC current is drawn from Vcntrl.

4. The circuit of claim 3, further comprising:

means for preventing the charging circuit from discharging the FET gate when Vpp exceeds the bias voltage.

5. The circuit of claim 4, wherein the charging circuit comprises a P-channel FET (Q4) having a gate electrode driven by Vpp_sel, a source electrode coupled to a bias voltage source, and a drain electrode coupled to a first diode for driving the N-channel FET gate.

6. The circuit of claim 5, wherein the charge removal circuit comprises a second N-channel FET (Q2) having a gate electrode, a drain electrode coupled to the gate of the N-channel FET and a source electrode coupled to Vcntrl, a second diode coupled between the gate of the second N-channel FET and Vcntrl and a capacitor coupled between Vpp_sel and the gate of the second N-channel FET.

7. The circuit of claim 6, wherein the preventing means includes a third N-channel FET (Q3) having a gate electrode coupled to the gate of the N-channel FET, a source electrode coupled to Vcntrl and a drain electrode coupled to the gate of the second N-channel FET.

8. The circuit of claim 7, further comprising a third diode coupled between the gate of the third N-channel FET and Vcntrl.

9. The circuit of claim 8, further comprising a resistor coupled between the first diode and the gate of the N-channel FET.

10. The circuit of claim 1, wherein Vpp_sel is removed at a predetermined normalization time.

11. A circuit for controlling a capacitive load, comprising:

an N-channel FET having a gate electrode, a source electrode coupled to a high voltage signal source Vss, wherein Vss comprises a negative going pulse train, and a drain electrode coupled to an output Vcntrl for controlling the load;

a charging circuit, responsive to a low voltage input signal Vss_sel, for charging the FET gate to a bias voltage greater than the FET'"'"'s threshold voltage while Vss is near zero volts and for maintaining the bias voltage on the FET gate until Vss_sel is removed;

a charge removal circuit, responsive to removal of Vss_sel, for removing the charge on the FET gate such that no substantial DC current is drawn from Vcntrl;

wherein the charging circuit comprises a P-channel FET (Q14) having a gate electrode driven by Vss_sel, a source electrode coupled to an intermediate voltage source, and a drain electrode coupled to the gate of the N-channel FET.

12. A circuit for controlling a capacitive load, comprising:

an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp comprises a positive going pulse train, and a source electrode coupled to an output Vcntrl for controlling the load; and

a gate control circuit, for controlling the voltage on the FET gate, wherein the gate control circuit includes

a charging circuit, responsive to a low voltage input signal Vpp_sel, for providing a bias voltage greater than Vpp to the FET gate while Vpp is near zero volts and for maintaining the bias voltage on the FET gate until Vpp_sel is removed, and

a discharging circuit, responsive to removal of the low voltage input signal, for removing charge from the FET gate such that no substantial DC current is drawn from Vcntrl.

13. The circuit of claim 12, wherein the charging circuit comprises a P-channel FET having a gate coupled to the low voltage input signal, a source coupled to a bias voltage source and its drain coupled to the N-channel FET gate;

and

wherein the discharging circuit comprises a second N-channel FET having a gate coupled to the low voltage input signal, a drain coupled to the N-channel FET gate and a source coupled to Vcntrl.

14. The circuit of claim 13, further comprising:

a parallel circuit comprising a capacitor and a diode coupled between the gates of the P-channel FET and the second N-channel FET.

15. The circuit of claim 13, further comprising a diode coupled between the drain of the second N-channel FET and Vcntrl for preventing overcharging of the N-channel FET gate if the N-channel FET is turned on when Vpp is greater than zero volts.

16. The circuit of claim 13, further comprising a diode coupled between the gate of the second N-channel FET and Vcntrl for preventing overcharging of the second N-channel FET gate.

17. The circuit of claim 12, further comprising a level translator for translating Vpp_sel to an intermediate voltage control signal.

18. The circuit of claim 17, wherein the level translator comprises:

a first circuit, responsive to Vpp_sel when Vpp_sel is high, for translating the low voltage signal to an intermediate control signal; and

a second circuit, responsive to Vpp_sel when Vpp_sel is low, for removing the intermediate control signal.

19. The circuit of claim 18, wherein each of the first circuit and the second circuits includes complementary elements, wherein the first circuit comprises:

a first FET driven by Vpp_sel;

a second FET driven by Vpp and connected in series with the first FET; and

a third FET, wherein the source of the third FET is connected to a voltage source greater than Vpp and the drain of the third FET provides the intermediate control signal;

wherein the third FET is turned on before Vpp_sel is applied;

wherein when Vpp_sel goes high, the first FET turns on, followed by the second FET, then the third FET of the second circuit turns on and the third FET of the first circuit turns off.

20. The circuit of claim 19, wherein each of the first circuit and the second circuit comprises a fourth FET connected in series between the first FET and the second FET, wherein the fourth FET is driven by a second bias voltage and reduces peak current during switching.

21. The circuit of claim 20, further comprising:

a resistor connected in series between the drain of third FET and the source of the second FET for reducing switch off time.

22. The circuit of claim 21, further comprising:

a fifth FET driven by the source of the second FET of the second circuit and a second resistor for reducing switch on time, whereon the drain of the fifth FET is connected to the drain of the third FET and the source of the fifth FET is connected to the second resistor; and

wherein the other side of the resistor is connected to Vpp.