Method for forming a printed circuit board and a printed circuit board formed thereby

• US 7,019,959 B2
• Filed: 03/28/2002
• Issued: 03/28/2006
• Est. Priority Date: 04/19/2001
• Status: Expired due to Fees

• Current Assignee: GUL Technologies Singapore Limited (Greenwich Pacific Pte Ltd.)
• Original Assignee: GUL Technologies Singapore Limited (Greenwich Pacific Pte Ltd.)
• Inventors: Chua, Ah Lim
• Primary Examiner(s): Thomas, Eric W.
• Application Number:
  US10/475,267
• Publication Number:
  US 20040124493A1
• Time in Patent Office: 1,461 Days
• Field of Search: 361/782, 361328-330, 361760-766, 361303-304, 361/306.1, 361/306.2, 361/306.3, 361312-313, 361323-326, 174/260
• US Class Current: 361/329
• CPC Class Codes: H05K 1/0263 High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board H05K1/0293 takes precedence
• CPC Class Codes: H05K 1/0265 characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/09672 Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236
• CPC Class Codes: H05K 2201/09736 Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
• CPC Class Codes: H05K 2203/0369 Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/4611 by laminating two or more circuit boards H05K3/4652 takes precedence

Abstract

Upper, inner and lower sections (182, 180 and 184) of a PCB (100) are formed with each section having a substrate (140, 150 and 160) having patterned layers of metallization (105 and 110, 115 and 120, and 125 and 130), respectively. Some of the patterned layers of metallization (110, 115, 120, and 125) have thicker portions (171, 173) and part (188) of portion (186), and thinner portions (172, 174, 187, 190, 191, 192 and 193). The resultant thinner portion (175 and 194) in the prepreg layers (145 and 155) with the respective thicker portions of metallization provide decoupling capacitors, while the resultant thicker portions (196 and 198), for example, provide a lower capacitance for improved trace impedance for the signal traces (191 and 192).

Claims

1. A multi-layered substrate comprising:

a dielectric layer having a substantially uniform dielectric constant, the dielectric layer having a first surface and a second surface, and the dielectric layer having thicker portions and thinner portions between the first and second surfaces;

a first conductive layer on the first surface of the dielectric layer; and

a second layer comprising a plurality of conductive pieces on the second surface of the dielectric layer,

wherein a first of the plurality of conductive pieces, one of the thicker portions of the dielectric layer, and the first conductive layer form a first capacitor with lower capacitance, and

wherein a second of the plurality of conductive pieces, one of the thinner portions of the dielectric layer, and the first conductive layer form a second capacitor with higher capacitance.

2. A multi-layered substrate in accordance with claim 1 wherein the first conductive layer comprises a plurality of conductive pieces,

wherein the first of the plurality of conductive pieces of the second layer, the one of the thicker portions of the dielectric layer, and a first of the plurality of conductive pieces of the first conductive layer form the first capacitor, and

wherein the second of the plurality of conductive pieces of the second layer, the one of the thinner portions of the dielectric layer, and a second of the plurality of conductive pieces of the first conductive layer form the second capacitor.

3. A multi-layered substrate in accordance with claim 2 wherein the first of the plurality of conductive pieces of the second layer, the one of the thicker portions of the dielectric layer, and the first of the plurality of conductive pieces of the first conductive layer are substantially aligned along a first common axis extending between the first conductive layer and the second layer.

4. A multi-layered substrate in accordance with claim 2 wherein the second of the plurality of conductive pieces of the second layer, the one of the thinner portions of the dielectric layer, and the second of the plurality of conductive pieces of the first conductive layer are substantially aligned along a second common axis extending between the first conductive layer and the second layer.

5. A multi-layered substrate in accordance with claim 2 wherein the first and second of the plurality of conductive pieces of the first conductive layer have substantially unequal thickness extending from a first common plane.

6. A multi-layered substrate in accordance with claim 2 wherein the first and second of the plurality of conductive pieces of the first conductive layer have substantially equal thickness extending from a first common plane.

7. A multi-layered substrate in accordance with claim 2 wherein the first and second of the plurality of conductive pieces of the second layer have substantially equal thickness extending from a common plane.

8. A multi-layered substrate in accordance with claim 2 wherein the first and second of the plurality of conductive pieces of the second layer have substantially unequal thickness extending from a common plane.

9. A printed circuit board comprising:

at least one dielectric layer having at least a first portion with a first thickness and having at least a second portion wit a second thickness, wherein the second thickness is different from the first thickness;

at least a first pair of metallization layers having the at least the first portion therebetween forming a first capacitor with a first value;

at least a second pair of metallization layers having the at least the second portion therebetween forming a second capacitor with a second value different from the first value.

10. A printed circuit board in accordance with claim 9 wherein the at least one dielectric layer comprises a contoured dielectric layer having a range of thickness including the first thickness and the second thickness to provide a range of capacitor values.

11. A printed circuit board in accordance with claim 9, wherein at least one of each of the first and second pairs of metallization layers are substantially aligned with a horizontal plane.

12. A substrate comprising:

a layer of dielectric material having a first surface and a second surface, wherein the second surface is opposite the first surface; and

a plurality of conductive portions comprising;

at least a first pair of the plurality of conductive portions,

wherein one of the first pair of the plurality of conductive portions being disposed in the layer of dielectric material proximal to the first surface, wherein at least part of the one of the first pair of the plurality of conductive portions extending from the first surface towards the second surface, and

wherein the other one of the first pair of the plurality of conductive portions being disposed proximal to the second surface and being spaced apart from the at least part of the one of the first pair of the plurality of conductive portions by a first distance; and

at least a second pair of the plurality of conductive portions,

wherein one of the second pair of the plurality of conductive portions being disposed in the layer of dielectric material proximal to the first surface, wherein at least part of the one of the second pair of the plurality of conductive portions extending from the first surface towards the second surface, and

wherein the other one of the second pair of conductive portions being disposed proximal to the second surface and being spaced apart from the at least part of the one of the second pair of conductive portions by a second distance, wherein the first distance is greater than the second distance.