Device and method for compensating defect in semiconductor memory
First Claim
1. A device for compensating a semiconductor memory defect, suitable for a semiconductor memory, said semiconductor memory including a control unit, an address decoder circuit, and a sensing circuit, said device comprising:
- a memory array, comprising a memory region having a plurality of memory cells, said memory array being coupled to said address decoder circuit and said sensing circuit for storing data, wherein if said memory array has a defect, said memory array is divided into a plurality of sub-memory regions, one of said plurality of sub-memory regions is defectless, and wherein said memory array is replaced with said defectless sub-memory region for storing data;
a selection circuit, coupled to said control unit, said selection circuit selecting one of said memory region and said defectless sub-memory region to store data; and
a first input address buffer, coupled to said control unit and said address decoder circuit, said first input address buffer including an address input port and an address output port, said address input port receiving a most significant bit address signal;
wherein if said memory array is defectless, said selection circuit outputs a selection signal to select said memory region to store data and makes said control unit control said address output port to output said most significant bit address signal to said address decoder circuit;
if said memory array has said defect, said selection circuit outputs a selection signal to select said defectless memory region to store data and makes said control unit control said address output port to output said selection signal to said address decoder circuit.
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Accused Products
Abstract
A device for compensating a semiconductor memory defect suitable for a semiconductor memory is provided. The device comprises: a memory array, the memory array having a memory region consisting of a plurality of memory cells, the memory array being coupled to the address decoder circuit and the sensing circuit for storing data, if the memory array has a defect, the memory array is divided into a plurality of sub-memory regions, wherein one of the plurality of sub-memory regions is defectless, the memory array is replaced by the defectless sub-memory regions for storing data. A selection circuit coupled to the control unit, selects one of the memory region and the defectless sub-memory region to store data. A first input address buffer coupled to the control unit and the address decoder circuit has an address input port and an address output port. The address input port receives a most significant bit address signal, wherein if the memory array is defectless, the selection circuit outputs a selection signal to select the memory region to store data and makes the control unit control the address output port to output the most significant bit address signal to the address decoder circuit. If the memory array has the defect, the selection circuit outputs a selection signal to select the defectless memory region to store data and makes the control unit control the address output port to output the selection signal to the address decoder circuit.
9 Citations
12 Claims
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1. A device for compensating a semiconductor memory defect, suitable for a semiconductor memory, said semiconductor memory including a control unit, an address decoder circuit, and a sensing circuit, said device comprising:
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a memory array, comprising a memory region having a plurality of memory cells, said memory array being coupled to said address decoder circuit and said sensing circuit for storing data, wherein if said memory array has a defect, said memory array is divided into a plurality of sub-memory regions, one of said plurality of sub-memory regions is defectless, and wherein said memory array is replaced with said defectless sub-memory region for storing data; a selection circuit, coupled to said control unit, said selection circuit selecting one of said memory region and said defectless sub-memory region to store data; and a first input address buffer, coupled to said control unit and said address decoder circuit, said first input address buffer including an address input port and an address output port, said address input port receiving a most significant bit address signal; wherein if said memory array is defectless, said selection circuit outputs a selection signal to select said memory region to store data and makes said control unit control said address output port to output said most significant bit address signal to said address decoder circuit; if said memory array has said defect, said selection circuit outputs a selection signal to select said defectless memory region to store data and makes said control unit control said address output port to output said selection signal to said address decoder circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for compensating a semiconductor memory defect, suitable for a semiconductor memory, said semiconductor memory including a memory region to store data for access and a plurality of address input ports for inputting an address signal, said address signal determining a location of said data in said memory region, said semiconductor memory including an identification code for representing a size of said semiconductor memory, said method comprising:
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determining whether said memory region of said semiconductor memory has a defect; wherein when said memory region of said semiconductor memory is found to be defective, said memory region is divided into a plurality of sub-memory regions, and wherein one of said plurality of sub-memory regions is defectless; and replacing said memory region with said defectless sub-memory region to store said data. - View Dependent Claims (11, 12)
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Specification