Variable programming of non-volatile memory

• US 7,020,017 B2
• Filed: 04/06/2004
• Issued: 03/28/2006
• Est. Priority Date: 04/06/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian, Wang, Chi-Ming
• Primary Examiner(s): Phung, Anh
• Assistant Examiner(s): Nguyen, Dang T.
• Application Number:
  US10/818,597
• Publication Number:
  US 20050219896A1
• Time in Patent Office: 721 Days
• Field of Search: 365/185.03, 365/185.14, 365/185.33, 365/185.24, 365/185.18, 365/185.22, 365/185.11
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

Claims

1. A method of programming non-volatile memory, comprising:

programming a first set of one or more non-volatile storage elements to a first physical state; and

programming a second set of one or more non-volatile storage elements to said first physical state, said first physical state includes a lower minimum voltage for said second set of one or more non-volatile storage elements than for said first set of one or more non-volatile storage elements.

2. A method according to claim 1, wherein:

said first physical state includes a first minimum threshold voltage for said first set and a second minimum threshold voltage for said second set, said second minimum threshold voltage is less than said first minimum threshold voltage.

3. A method according to claim 2, wherein:

said step of programming said first set to said first physical state includes programming said first set using a first target level; and

said step of programming a second set includes programming said second set using a second target level.

4. A method according to claim 3, wherein:

said step of programming said first set includes verifying programming of said first set to said first physical state, wherein verifying includes determining whether a threshold voltage of said one or more non-volatile storage elements of said first set has reached said first target level; and

said step of programming said second set includes verifying programming of said second set to said first physical state, wherein verifying includes determining whether a threshold voltage of said one or more non-volatile storage elements of said second set has reached said second target level.

5. A method according to claim 4, wherein:

said first target level is equal to said first minimum threshold voltage; and

said second target level is equal to said second minimum threshold voltage.

6. A method according to claim 1, wherein:

said step of programming said second set is performed subsequent to said step of programming said first set.

7. A method according to claim 6, wherein:

said first set of non-volatile storage elements and said second set of non-volatile storage elements are part of a NAND string;

said second set of one or more non-volatile storage elements is coupled to a particular word line for said NAND string; and

said first set of one or more non-volatile storage elements is coupled to other word lines for said NAND string.

8. A method according to claim 7, wherein:

said particular word line is a last word line to be programmed for said NAND string during a program operation.

9. A method according to claim 1, wherein:

said step of programming said first set includes intending to apply a first maximum program voltage to program said first set to said first physical state; and

said step of programming said second set includes intending to apply a second maximum program voltage to program said second set to said first physical state, said second maximum program voltage is less than said first maximum program voltage.

10. A method according to claim 1, further comprising:

reading said first set, said step of reading includes applying one or more first read values to determine if said one or more storage elements of said first set are programmed to said first physical state; and

reading said second set, said step of reading includes applying one or more second read values to determine if said one or more storage elements of said second set are programmed to said second physical state; and

wherein said one or more second read values are less than said one or more first read values.

11. A method according to claim 1, wherein:

said first physical state corresponds to a highest threshold voltage range of said first set used to represent physical states and a highest threshold voltage range of said second set used to represent physical states.

12. A method according to claim 1, wherein:

said first set of one or more non-volatile storage elements and said second set of one or more non-volatile storage elements are sets of one or more binary non-volatile storage elements.

13. A method according to claim 1, wherein:

said first set of one or more non-volatile storage elements and said second set of one or more non-volatile storage elements are sets of one or more multi-state non-volatile storage elements.

14. A method according to claim 1, wherein:

said first set of one or more non-volatile storage elements and said second set of one or more non-volatile storage elements are flash memory devices.

15. A method according to claim 1, wherein:

said first set and said second set are part of an array of flash memory devices;

said array is in communication with a host system; and

said array is removable from said host system.

16. A method of programming non-volatile memory, comprising:

programming a first set of one or more non-volatile storage elements to a first physical state using a first target minimum voltage for said first physical state; and

programming a second set of one or more non-volatile storage elements to said first physical state using a second target minimum voltage for said first physical state, said second target minimum voltage is below said first target minimum voltage.

17. A method according to claim 16, wherein:

said first target minimum voltage is a first minimum threshold voltage level; and

said second target minimum voltage is a second minimum threshold voltage level.

18. A method according to claim 16, wherein:

said step of programming a first set of one or more non-volatile storage elements includes verifying programming of said first set to said first physical state using said first target minimum voltage;

said step of programming a second set of one or more non-volatile storage elements includes verifying programming of said second set to said first physical state using said second target minimum voltage.

19. A method according to claim 16, wherein:

said step of programming said second set is performed subsequent to said step of programming said first set.

20. A method according to claim 19, wherein:

said first set and said second set are part of a NAND string;

said second set of one or more non-volatile storage elements is coupled to a particular word line for said NAND string; and

said second set of one or more non-volatile storage elements is coupled to other word lines of said NAND string.

21. A method according to claim 20, wherein:

said particular word line is a last word line to be programmed for said string during a program operation.

22. A method according to claim 16, wherein:

said first physical state includes a lower minimum threshold voltage for said first set of non-volatile storage elements than for said second set of non-volatile storage elements.

23. A method according to claim 16, wherein:

said first set of one or more non-volatile storage elements and said second set of one or more non-volatile storage elements are sets of one or more multi-state flash non-volatile storage elements.

24. A method according to claim 16, wherein:

said first set and said second set are part of an array of flash memory devices;

said array is in communication with a host system; and

said array is removable from said host system.

25. A non-volatile memory system, comprising:

a set of non-volatile storage elements, said set of non-volatile storage elements includes a first subset of non-volatile storage elements storing data through a first set of physical states and a second subset of non-volatile storage elements storing data through said first set of physical states, one or more of said first set of physical states are at lower voltages for said second subset of non-volatile storage elements than for said first subset of non-volatile storage elements; and

managing circuitry in communication with said non-volatile storage elements.

26. A non-volatile memory system according to claim 25, wherein:

said one or more of said first set of physical states include lower minimum threshold voltages for said second subset of non-volatile storage elements than for said first subset of non-volatile storage elements.

27. A non-volatile memory system according to claim 25, wherein:

said managing circuitry uses one or more first target levels to program said first subset of non-volatile storage elements to said one or more of said first set of physical states and one or more second target levels to program said second subset of non-volatile storage elements to said one or more of said first set of physical states.

28. A non-volatile memory system according to claim 27, wherein:

said one or more second target levels are lower than said one or more first target levels.

29. A non-volatile memory system according to claim 28, wherein:

said one or more first target levels are one or more minimum threshold voltages of said one or more of said first set of physical states for said first subset of non-volatile storage elements; and

said one or more second target levels are one or more minimum threshold voltages of said one or more of said first set of physical states for said second subset of non-volatile storage elements.

30. A non-volatile memory system according to claim 25, wherein:

said set of non-volatile storage elements is a set of multi-state flash non-volatile storage elements.

31. A non-volatile memory system according to claim 25, wherein:

said managing circuitry includes at least one of a controller, a state machine, and sense amplifiers.

32. A non-volatile memory system according to claim 25, wherein:

said set of non-volatile storage elements are part of an array of flash memory devices;

said array is in communication with a host system; and

said array is removable from said host system.

33. A non-volatile memory system, comprising:

a first set of storage elements coupled to a first word line, said first set of storage elements having a first set of physical states;

a second set of storage elements coupled to a second word line, said second word line being programmed subsequent to said first word line during a program operation, said second set of storage elements having said first set of physical states;

a managing circuit adapted to program said first set of storage elements and said second set of storage elements, said managing circuit programs said first set of storage elements to one or more of said first set of physical states using one or more first target minimum voltages for said first set of physical states, said managing circuit programs said second set of storage elements to said one or more of said first set of physical states using one or more second target minimum voltages for said first set of physical states, said one or more second target minimum voltages are lower than said one or more first target minimum voltages.

34. A non-volatile memory system according to claim 33, wherein:

said one or more of said first set of physical states include lower minimum threshold voltages for said second subset of non-volatile storage elements than for said first subset of non-volatile storage elements.

35. A non-volatile memory system according to claim 33, wherein:

said first set of non-volatile storage elements are multi-state flash memory devices.

36. A non-volatile memory system, comprising:

means for programming a first set of one or more non-volatile storage elements to a first physical state using a first target minimum voltage for said first physical state; and

means for programming a second set of one or more non-volatile storage elements to said first physical state using a second target minimum voltage for said first physical state, said second target minimum voltage is below said first target minimum voltage.

37. A method of programming non-volatile memory, comprising:

programming a first non-volatile storage element to a first physical state;

verifying programming of said first non-volatile storage element to said first physical state using a first value of a verification parameter to determine whether said first non-volatile storage element has reached said first physical state;

programming a second non-volatile storage element to said first physical state; and

verifying programming of said second non-volatile storage element to said first physical state using a second value of said verification parameter to determine whether said second non-volatile storage element has reached said first physical state.

38. A method according to claim 37, wherein:

said step of programming said first non-volatile storage element includes determining that said first non-volatile storage element is not coupled to a last word line to be programmed for a NAND string and accessing said first value of said verification parameter in response to said determining; and

said step of programming said second non-volatile storage element includes determining that said second non-volatile storage element is coupled to said last word line to be programmed for said NAND string and accessing said second value of said verification parameter in response to said determining.

39. A method according to claim 38, further comprising:

increasing a program voltage and repeating said steps of programming said first non-volatile storage element and verifying programming of said first non-volatile storage element if said step of verifying does not verify said first non-volatile storage element as programmed to said first physical state; and

increasing said program voltage and repeating said steps of programming said second non-volatile storage element and verifying programming of said second non-volatile storage element if said step of verifying does not verify said second non-volatile storage element as programmed to said first physical state.

40. A method according to claim 39, wherein:

said step of verifying programming of said first non-volatile storage element using said first value of said verification parameter includes verifying that said first non-volatile storage element is programmed to said first physical state when a threshold voltage of said first non-volatile storage element is at or above first level; and

said step of verifying programming of said second non-volatile storage element using said second value of said verification parameter includes verifying that said second non-volatile storage element is programmed to said first physical state when a threshold voltage of said second non-volatile storage element is at or above a second level;

wherein said second level is less than said first level.

41. A method of programming non-volatile memory, comprising:

applying a program voltage to a non-volatile storage element coupled to a first word line, said non-volatile storage element is part of a string of non-volatile storage elements;

determining whether said non-volatile storage element is programmed to a target state; and

increasing said program voltage and applying said increased program voltage to said non-volatile storage element if said non-volatile storage element is not programmed to said target state, said step of increasing includes increasing said program voltage by a first amount if said first word line is a last word line to be programmed for said string during a program operation, and increasing said program voltage by a second amount if said first word line is not a last word line to be programmed for said string during a program operation.

42. A method according to claim 41, wherein:

said first amount is greater than said second amount.

43. A method according to claim 42, wherein:

said string is a NAND string; and

said non-volatile storage element is a multi-state flash storage element.