Measuring and correcting sense amplifier and memory mismatches using NBTI
First Claim
Patent Images
1. A memory circuit comprising:
- a sensing circuit including a cross-coupled pair of transistors; and
a control block responsive to detection of a sensing offset of the sensing circuit, the control block at least partially compensating for the detected sensing offset by selectively exposing one of the transistors to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor.
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Abstract
Post-manufacture compensation for a sensing offset can be provided, at least in part, by selectively exposing one of a pair of cross-coupled transistors in a sense amplifier to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. Such exposure may be advantageously provided in situ by causing the sense amplifier to sense values purposefully skewed toward a predominate value selected to cause the compensating shift. In some realizations, purposefully skewed values (e.g., value and value_1) are introduced directly into the sense amplifier. In some realizations, an on-chip test block is employed to identify and characterize sensing mismatch.
50 Citations
68 Claims
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1. A memory circuit comprising:
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a sensing circuit including a cross-coupled pair of transistors; and a control block responsive to detection of a sensing offset of the sensing circuit, the control block at least partially compensating for the detected sensing offset by selectively exposing one of the transistors to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method of operating a semiconductor memory, the method comprising:
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detecting a sensing offset in a sensing circuit that includes a cross-coupled pair of transistors; and at least partially compensating for the detected sensing offset by selectively exposing one of the transistors to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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44. A method of compensating for accumulated data-dependent post-manufacture creep in a characteristic of one or more devices of a sensing circuit of a semiconductor memory, the method comprising:
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performing an in situ test operation that characterizes a sensing offset of the sensing circuit; and selectively exposing one of the devices to a bias voltage selected to cause a compensating shift in a characteristic thereof and thereby at least partially correct the sensing offset. - View Dependent Claims (45, 46, 47, 48, 49, 50)
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51. An integrated circuit comprising:
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a differential circuit susceptible to an accumulated data-dependent post-manufacture creep in a characteristic of a first device thereof, the characteristic creep affecting a sensing offset of the differential circuit; and a biasing circuit introducible into the differential circuit to cause an accumulated compensating shift in the characteristic of a second device thereof and thereby at least partially reducing the sensing offset. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59, 60)
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- 61. An integrated circuit chip that compensates, in situ, for a sensing offset at least in part by selectively exposing one of a pair of cross-coupled transistors to a bias voltage selected to cause a compensating shift in a characteristic of the exposed transistor.
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68. An apparatus comprising:
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means for sensing a differential pair in a semiconductor memory; means for at least partially compensating for a sensing offset exhibited by the sensing means, the compensating means causing an accumulated data-dependent effect on a characteristic of at least one device of the sensing means, wherein the compensating means, when employed, at least partially compensates for the sensing offset.
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Specification