Frequency searcher and frequency-locked data demodulator using a programmable rotator

• US 7,020,225 B2
• Filed: 12/07/2001
• Issued: 03/28/2006
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Black, Peter J., Glazko, Serguei A., Sindhushayana, Nagabhushana T.
• Primary Examiner(s): Vanderpuye, Kenneth
• Assistant Examiner(s): Perilla, Jason M.
• Application Number:
  US10/017,073
• Publication Number:
  US 20020114405A1
• Time in Patent Office: 1,572 Days
• Field of Search: 375/354, 375/371, 375/373, 375/376, 375/316, 375/327, 375/344, 375/362, 375/147, 375/148, 375/375
• US Class Current: 375/344
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04L 2027/0055 single phase
• CPC Class Codes: H04L 2027/0065 Frequency error detectors H04L2027/0067 takes precedence
• CPC Class Codes: H04L 2027/0087 Out-of-band signals, (e.g. pilots)
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence

Abstract

A searcher is centered on frequency bins to search for an incoming signal. The frequency locked loop generates an initial phase signal and a phase increment signal that are input to an accumulator. The accumulator accumulates the phase increments over a predetermined interval. After the interval, the accumulator generates a control signal that instructs a rotator to perform a phase rotation function.

Claims

1. A method of finding a signal having a deviation from an expected frequency, the method comprising:

first phase rotating a signal to partially reduce a phase error of the signal and produce a partially rotated output signal;

accumulating a plurality of chips from the partially rotated output signal to form segments of the partially rotated output signal;

second phase rotating the segments of the partially rotated output signal to further reduce a phase error of the segments by adjusting the phase over each segment; and

generating a phase increment signal based on the phase error of the segments, the first phase rotating the signal to partially reduce the phase error of the signal based on an accumulation of the phase increment signal.

2. A method in accordance with claim 1, further comprising:

generating a phase increment signal based on the phase error of the segments the first phase rotating the signal to partially reduce the phase error of the signal based on the phase increment signal.

3. A method in accordance with claim 2, wherein the first phase rotating the signal to partially reduce the phase error of the signal comprises compensating for instantaneous signal phase changes over each segment.

4. A method in accordance with claim 3, wherein the second phase rotating the signal to further reduce the phase error of the segments comprises compensating for instantaneous signal phase changes over each segment by partially phase rotating the signal based on an average phase of the signal over multiple chips.

5. A searcher for finding the frequency of a received signal comprising a plurality of segments, the searcher comprising:

a first phase rotator configured to phase rotate a signal to partially reduce a phase error of the signal and produce a first phase rotator output signal;

an accumulator configured to accumulate a plurality of chips from the first phase rotator output signal to form segments of the first phase rotator output signal;

a second rotator configured to phase rotate the segments of the first phase rotator output signal to further reduce a phase error of the segments by adjusting the phase over each segment; and

wherein the second rotator is implemented within a frequency locked loop producing a phase increment signal based on the phase error of the segments, the first phase rotator configured to phase rotate the signal based on an accumulation of the phase increment signal.

6. A searcher in accordance with claim 5, wherein the second rotator is implemented within a frequency locked loop producing a phase increment signal based on the phase error of the segments, the first phase rotator configured to phase rotate the signal based on the phase increment signal.

7. A searcher in accordance with claim 6, wherein the first phase rotator is configured to partially reduce the phase error of the signal by compensating for instantaneous signal phase changes over each segment.

8. A searcher in accordance with claim 7, wherein the second phase rotator is configured to partially phase rotate the segments based on an average phase of the signal over multiple chips.

9. A searcher in accordance with claim 8, wherein the first phase rotator is a high-speed low-resolution phase rotator and the second phase rotator is a low-speed high-resolution phase rotator.

10. A searcher in accordance with claim 9, wherein the first phase rotator is a hardware rotator and the second phase rotator is a DSP rotator.

11. A searcher for finding the frequency of a received signal comprising a phase error, the searcher comprising:

a frequency locked loop that generates a phase increment signal in response to the phase error of the received signal;

a programmable rotator coupled to the frequency locked loop, the programmable rotator performing a phase rotation function;

a phase error accumulator accumulating results of the phase increment signals from the frequency locked loop and generating a control signal that instructs the programmable rotator to perform the phase rotation function; and

a shift register coupled between the phase error accumulator and the programmable rotator, the shift register truncating a predetermined number of bits of the control signal,

wherein the frequency locked loon further comprises means for generating an initial phase signal that is coupled to the programmable rotator and initializes the programmable rotator to a predetermined starting phase.

12. The searcher of claim 11 wherein the programmable rotator is an 8-Phase Shift Keying rotator.

13. The searcher of claim 11 wherein the programmable rotator is a Quadrature Phase Shift Keying rotator.

14. The searcher of claim 11 wherein the phase error accumulator accumulates phase increment signals over a 64-chip interval.

15. The searcher of claim 13 wherein the frequency locked loop further comprises means for generating an initial phase signal that is coupled to the Quadrature Phase Shift Keying programmable rotator and initializes the Quadrature Phase Shift Keying programmable rotator to a predetermined starting phase.