Technique for creating extended bit timer on a time processing unit
First Claim
1. A method for implementing an extended bit timer with a timer processing unit (TPU) without using channel hardware of the TPU, comprising the steps of:
- periodically reading a timer to determine a value of the timer;
determining if the value of the timer is equal to or between a first count and a second count;
determining if the value of the timer is equal to or greater than a third count;
incrementing a counter after rollover of the timer has occurred;
de-asserting a coherency flag after the timer transitions through the first count;
asserting the coherency flag after the value of the timer transitions through the third count;
combining the value of the timer with the value of the counter to provide a current count; and
checking the coherency flag and the value of the timer and adjusting the current count when the coherency flag is asserted and the value of the timer is equal to or between the first and second counts.
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Abstract
A technique for implementing an extended bit timer with a time processing unit (TPU), without using the channel hardware of the TPU includes a number of steps. A timer of the TPU is periodically read to determine the value of the timer. A counter is incremented when rollover of the timer has occurred and a coherency flag is de-asserted after the timer transitions through a first count. The coherency flag is asserted after the value of the timer transitions through a third count and the value of the timer is combined with the value of the counter to provide a current count. When the coherency flag is asserted and the value of the timer is equal to or between the first and second counts, the current count is adjusted.
31 Citations
19 Claims
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1. A method for implementing an extended bit timer with a timer processing unit (TPU) without using channel hardware of the TPU, comprising the steps of:
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periodically reading a timer to determine a value of the timer; determining if the value of the timer is equal to or between a first count and a second count; determining if the value of the timer is equal to or greater than a third count; incrementing a counter after rollover of the timer has occurred; de-asserting a coherency flag after the timer transitions through the first count; asserting the coherency flag after the value of the timer transitions through the third count; combining the value of the timer with the value of the counter to provide a current count; and checking the coherency flag and the value of the timer and adjusting the current count when the coherency flag is asserted and the value of the timer is equal to or between the first and second counts. - View Dependent Claims (2, 3, 4, 5)
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6. A system, comprising:
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a central processing unit (CPU); a time processing unit (TPU) including a plurality of channels; a dual-ported memory coupled to the CPU and the TPU; and code for instructing the CPU to perform the steps of; periodically reading a timer of the TPU to determine a value of the timer; determining if the value of the timer is equal to or between a first count and a second count; determining if the value of the timer is equal to or greater than a third count; incrementing a counter created within the dual-ported memory after rollover of the timer has occurred; de-asserting a coherency flag created within the dual-ported memory after the timer transitions through the first count; asserting the coherency flag after the value of the timer transitions through the third count; combining the value of the timer with the value of the counter to provide a current count; and checking the coherency flag and the value of the timer and adjusting the current count when the coherency flag is asserted and the value of the timer is equal to or between the first and second counts. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A system, comprising:
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a central processing unit (CPU); a time processing unit (TPU) including a plurality of channels; a dual-ported memory coupled to the CPU and the TPU; and code for instructing the TPU to perform the steps of; periodically reading a timer of the TPU to determine a value of the timer; determining if the value of the timer is equal to or between a first count and a second count; determining if the value of the timer is equal to or greater than a third count; incrementing a counter created within the dual-ported memory after rollover of the timer has occurred; de-asserting a coherency flag created within the dual-ported memory after the timer transitions through the first count; asserting the coherency flag after the value of the timer transitions through the third count; combining the value of the timer with the value of the counter to provide a current count; and checking the coherency flag and the value of the timer and adjusting the current count when the coherency flag is asserted and the value of the timer is equal to or between the first and second counts. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification