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Method and apparatus for adaptive timing optimization of an integrated circuit design

  • US 7,020,589 B1
  • Filed: 09/26/2001
  • Issued: 03/28/2006
  • Est. Priority Date: 09/29/2000
  • Status: Expired due to Fees
First Claim
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1. A method of optimizing a functional block within a netlist of an integrated circuit design, the method comprising:

  • (a) defining a continuous set of possible combinations in which each combination in the set satisfies a predetermined criteria and assigning a corresponding delay value to each of a plurality of pins of the block, wherein each pin corresponds to a respective signal path through the block and wherein the delay values together form a delay value combination that is selected from the continuous set of possible combinations; and

    (b) generating a circuit configuration for the block with a plurality of logic cells that are interconnected in the netlist such that the respective signal paths through the block have delays based on the corresponding delay values assigned in step (a).

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