Write back cache memory control within data processing system

• US 7,020,751 B2
• Filed: 07/25/2002
• Issued: 03/28/2006
• Est. Priority Date: 01/19/1999
• Status: Expired due to Term

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Kershaw, Daniel
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US10/201,955
• Publication Number:
  US 20020184449A1
• Time in Patent Office: 1,342 Days
• Field of Search: 711/133, 711/141, 711/143, 711/159, 711/105
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/127 using additional replacement algorithms
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A data processing system 2 is described including a cache memory 8 and a plurality of DRAM banks 16, 18, 20, 22. A victim select circuit 32 within a cache controller 10 selects victim cache storage lines 28 upon a cache miss such that unlocked cache storage lines are selected in preference to locked cache storage lines, non-dirty cache storage lines are selected in preference to dirty cache storage lines, and cache storage lines requiring a write back to a non-busy DRAM bank are selected in preference to cached storage lines requiring a write back to a busy DRAM storage bank. A DRAM controller 24 is provided that continuously performs a background processing operation whereby dirty cache storage lines 28 within a cache memory 8 are written back to their respective DRAM banks 16, 18, 20, 22 when these are not busy performing other operations and when the cache storage line has a least recently used value below a certain threshold. A bus arbitration circuit 12 is provided that re-arbitrates bus master priorities in dependence upon determined latencies for respective memory access requests. As an example, if a high priority memory access request results a cache miss, with a lower priority memory access request resulting in a cache hit, then the lower priority memory access request will be re-arbitrated to be performed ahead of the normally higher priority memory access request and may be finished before that higher priority memory access request starts to return data words to a data bus 14.

Claims

1. A data processing apparatus comprising:

(i) a write back cache memory having a plurality of cache storage lines;

(ii) at least one main memory unit operable to store data words to be cached within said cache memory, a cache storage line being dirty if it contains any data words that have been changed since they were transferred from said at least one main memory unit to said cache storage line; and

(iii) a background operation control circuit for triggering writing back of data words from dirty cache storage lines to said at least one main memory unit as a background process, cache storage lines written back using said background process becoming not dirty and continuing to store said data words that were written back,

wherein a main memory unit is busy when it is exchanging one or more data words with said cache memory, said background operation control circuit being operable not to trigger write back operations to a busy main memory unit.

2. Data processing apparatus as claimed in claim 1, wherein said at least one warn memory unit comprises a plurality of main memory units.

3. Data processing apparatus as claimed in claim 2, wherein said plurality of main memory units are operable to independently and concurrently transfer data words to said cache memory.

4. Data processing apparatus as claimed in claim 1, wherein said background operation control circuit is responsive to how recently data words from a dirty cache storage line were used when determining whether said dirty cache storage line should be written back to said at least one main memory unit, dirty cache storage lines more recently used than a threshold level not being written back to said at least one main memory unit.

5. Data processing apparatus as claimed in claim 1, wherein said at least one main memory unit is a bank of dynamic random access memory.

6. Data processing apparatus as claimed in claim 1, wherein said at least one main memory unit is provided together with said cache memory on an integrated circuit.

7. Data processing apparatus as claimed in claim 6, comprising at least one data word requesting unit that may request exchange of one or more data words with said cache memory, said at least one data word requesting unit being also provided on said integrated circuit.

8. Data processing apparatus as claimed in claim 7, wherein said at least one data word requesting unit includes a central processing unit.

9. Data processing apparatus as claimed in claim 7, wherein said at least one said data word requesting unit includes a video display driving circuit.

10. A data processing method comprising the steps of:

(i) storing data words within a plurality of cache storage lines of a write back cache memory;

(ii) storing in at least one main memory unit said data words to be cached within said cache memory, a cache storage line being dirty if it contains any data words that have been changed since they were transferred from said at least one main memory unit to said cache storage line; and

(iii) writing back data words from dirty cache storage lines to said at least one main memory unit as a background process, cache storage lines written back using said background process becoming not dirty and continuing to store said data words that were written back,

wherein when a main memory unit is busy is exchanging one or more data words with said cache memory write back operations are not triggered.