Techniques for reducing the rate of instruction issuance

• US 7,020,767 B2
• Filed: 02/23/2001
• Issued: 03/28/2006
• Est. Priority Date: 11/13/1998
• Status: Expired due to Term

• Current Assignee: U.S. District Court for the Southern District of Florida.
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Alverson, Gail A., Callahan, Charles David II, Kaplan, Laurence S., Korry, Richard D., Coatney, Susan L.
• Primary Examiner(s): Chan, Eddie
• Assistant Examiner(s): Li, Aimee
• Application Number:
  US09/792,426
• Publication Number:
  US 20020038332A1
• Time in Patent Office: 1,859 Days
• Field of Search: 712/227, 712/107, 718/106, 718/107
• US Class Current: 712/227
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

A method and system in a multithreaded processor for processing events without interrupt notifications. In one aspect of the present invention, an operating system creates a thread to execute on a stream of the processor. During execution of the thread, the thread executes a loop that determines whether an event has occurred and, in response to determining whether an event has occurred, assigns a different thread to process the event so that multiple events can be processed in parallel and so that interrupts are not needed to signal that the event has occurred. Another aspect of the present invention provides a method and system for processing asynchronously occurring events without interrupt notifications. To achieve this processing, a first thread is executed to generate a notification that the event has occurred upon receipt of the asynchronously occurring event. A second thread is also executed that loops determining whether a notification has been generated and, in response to determining that a notification has been generated, performing the processing necessary for the event.

Claims

1. A method in a computer for reducing the rate at which a program executes instructions by determining when the rate of execution should be reduced, and when it is determined that the rate of execution should be reduced executing an instruction to access data in memory, the data pointed to by a chain of forwarding words, so that subsequent instructions are not executed until a memory subsystem resolves the chain of forwarding words.

2. The method of claim 1 wherein the number of forwarding words in the chain is adjusted to effect a change in the rate at which the program executes instructions.

3. The method of claim 1 wherein the instruction is within a loop to effectively reduce the rate at which the loop is executed.

4. The method of claim 1 wherein the computer has a multithreaded processor.

5. The method of claim 1 wherein the computer starts execution of an instruction of another program during resolution of the chain of forwarding words.

6. The method of claim 5 wherein the computer has a processor that supports simultaneous execution of threads.

7. The method of claim 5 wherein the number of forwarding words in the chain affects the rate at which the program executes instructions.

8. The method of claim 7 wherein the rate of issuing instructions of the other program increases as a result of increasing the number of forwarding words in the chain.

9. A method in a computer system for reducing the rate at which a program executes instructions by determining when the rate of execution should be reduced, and when it is determined that the rate of execution should be reduced executing an operation to perform a synchronized access to a word of memory that will eventually fail so that the issuing of new instructions is deferred until after receiving notification of the failure.

10. The method of claim 9 including re-executing the operation a predetermined number of times to control the rate at which the program executes instructions.

11. The method of claim 9 wherein the failure of the operation is indicated by raising a retry-limit exception.

12. The method of claim 11 wherein the program disables a trapping of the retry-limit exception so that a thread that issued the operation can handle the exception.

13. A method in a computer system for decreasing a rate of issuing instructions of a program, the computer system supporting simultaneous execution of more than one program, each program having instructions, the method comprising:

determining when the rate of execution should be decreased;

when it is determined that the rate of execution should be decreased, issuing an instruction of the program whose rate of issued instructions is to be decreased, the instruction for accessing memory of the computer system wherein the accessing is for decreasing the rate of issued instructions for the program;

while the memory is being accessed during execution of the issued instruction of the program, issuing an instruction of an other program; and

when the access to the memory is complete, issuing another instruction of the program

wherein the instruction for accessing memory accesses a chain of forwarding words so that access to memory is not complete until resolution of the chain of forwarding words.

14. The method of claim 13 wherein the rate of issuing instructions for the other program increases as a result of the decreased rate of issuing instructions of the program.

15. The method of claim 13 including repeating the issuance of the instruction for accessing memory to further decrease the rate of issuing instructions.

16. The method of claim 13 wherein a number of forwarding words in the chain is changed to affect the rate of issued instructions for the program.

17. The method of claim 13 wherein the program is part of an operating system.

18. A method in a computer system for decreasing a rate of issuing instructions of a program, the computer system supporting simultaneous execution of more than one program, each program having instructions, the method comprising:

determining when the rate of execution should be decreased;

when it is determined that the rate of execution should be decreased, issuing an instruction of the program whose rate of issued instructions is to be decreased, the instruction for accessing memory of the computer system wherein the accessing is for decreasing the rate of issued instructions for the program;

while the memory is being accessed during execution of the issued instruction of the program, issuing an instruction of an other program; and

when the access to the memory is complete, issuing another instruction of the program

wherein the instruction is for synchronized access to a word of memory and the access to memory is not complete until the synchronized access is determined to have failed.

19. The method of claim 18 wherein the synchronized access fails when a number of attempts to access memory exceeds a limit.

20. The method of claim 18 wherein the synchronized access fails because a retry-limit is exceeded.

21. The method of claim 20 including disabling trapping of a retry-limit exception so that the program can handle the exception.

22. The method of claim 18 wherein the computer system is based on a multithreaded architecture.

23. The method of claim 18 including after the instruction completes, reissuing the instruction to further decrease the rate of issuing instructions of the program.

24. A computer system for decreasing a rate of issuing instructions of a program, the computer system supporting simultaneous execution of more than one program, comprising:

means for determining when the rate of execution should be decreased;

means for issuing an instruction of the program whose rate of issued instructions is to be decreased, the instruction including a memory operation so that another program can have its instructions issued at an increased rate during execution of the memory operation; and

means for issuing instructions of another program while memory is being accessed during execution of the issued instruction of the program

wherein the memory operation accesses a chain of forwarding words so that access to memory is not complete until resolution of the chain of forwarding words.

25. The computer system of claim 24 wherein issuing of other instructions of the program is deferred until access to memory is completed.

26. The computer system of claim 24 wherein a number of forwarding words in the chain is altered to affect the rate of issued instructions for the program.

27. The computer system of claim 24 wherein the program is part of an operating system.

28. A computer system for decreasing a rate of issuing instructions of a program, the computer system supporting simultaneous execution of more than one program, comprising:

means for determining when the rate of execution should be decreased;

means for issuing an instruction of the program whose rate of issued instructions is to be decreased, the instruction including a memory operation so that another program can have its instructions issued at an increased rate during execution of the memory operation; and

means for issuing instructions of another program while memory is being accessed during execution of the issued instruction of the program

wherein the memory operation is for synchronized access to a word of memory and the access to memory is not complete until the synchronized access is determined to have failed.

29. The computer system of claim 28 wherein the synchronized access fails when a number of attempts to access memory exceeds a limit.

30. The computer system of claim 28 wherein the synchronized access fails because a retry-limit is exceeded.

31. The computer system of claim 30 including disabling trapping of a retry-limit exception so that the program can handle the exception.

32. The computer system of claim 28 wherein the computer system has a multithreaded architecture.

33. The computer system of claim 28 including after the instruction completes, reissuing the instruction to further increase the rate of issuing instructions of the other program.

34. A computer-readable medium containing instructions for controlling a computer system to decrease a rate of issuing instructions of a program, by a method comprising:

determining when the rate of execution should be decreased;

when it is determined that the rate of execution should be decreased, issuing an instruction of the program whose rate of issued instructions is to be decreased, the instruction for accessing memory of the computer system wherein the accessing is for the purpose of decreasing the rate of issued instructions for the program; and

while the memory is being accessed during execution of the issued instruction of the program, issuing instructions for other programs to effect increasing the rate of issuing instructions of those other program

wherein the instruction for accessing memory accesses a chain of forwarding words so that access to memory is not complete until resolution of the chain of forwarding words.

35. The computer-readable medium of claim 34 wherein the issuing of other instructions of the program is deferred until the access to memory is completed.

36. The computer-readable medium of claim 34 wherein a number of forwarding words in the chain is changed to affect the rate of issued instructions for the program.

37. The computer-readable medium of claim 34 wherein the program is part of an operating system.

38. A computer-readable medium containing instructions for controlling a computer system to decrease a rate of issuing instructions of a program, by a method comprising:

determining when the rate of execution should be decreased;

when it is determined that the rate of execution should be decreased, issuing an instruction of the program whose rate of issued instructions is to be decreased, the instruction for accessing memory of the computer system wherein the accessing is for the purpose of decreasing the rate of issued instructions for the program; and

while the memory is being accessed during execution of the issued instruction of the program, issuing instructions for other programs to effect increasing the rate of issuing instructions of those other program

wherein the instruction is for synchronized access to a word of memory and the access to memory is not complete until the synchronized access is determined to have failed.

39. The computer-readable medium of claim 38 wherein the synchronized access fails when a number of attempts to access memory exceeds a limit.

40. The computer-readable medium of claim 38 wherein the synchronized access fails because a retry-limit is exceeded.

41. The computer-readable medium of claim 40 including disabling trapping of a retry-limit exception so that the program can handle the exception.

42. The computer-readable medium of claim 38 wherein the computer system is based on a multithreaded architecture.

43. The computer-readable medium of claim 38 including after the instruction completes, reissuing the instruction to further decrease the rate of issuing instructions of the program.

44. A method in a computing system for implementing an interrupt-free operating system comprising:

checking for an occurrence of an event;

determining that the event will not occur frequently relative to the time it takes to process the event and that the rate of issuing instructions should be reduced;

when the determination is made, executing an instruction for accessing memory that will reduce the rate of issuing instructions; and

after executing the instruction, checking for the occurrence of the event

wherein the instruction for accessing memory accesses a chain of forwarding words so that access to memory is not complete until resolution of the chain of forwarding words.

45. The method of claim 44 wherein the number of forwarding words in the chain is altered to affect the rate of issued instructions for the program.

46. A method in a computing system for implementing an interrupt-free operating system comprising:

checking for an occurrence of an event;

determining that the event will not occur frequently relative to the time it takes to process the event and that the rate of issuing instructions should be reduced;

when the determination is made, executing an instruction for accessing memory that will reduce the rate of issuing instructions; and

after executing the instruction, checking for the occurrence of the event

wherein the instruction is for synchronized access to a word of memory and the access to memory does not complete until the synchronized access is determined to have failed.

47. The method of claim 46 wherein the synchronized access fails when a number of attempts to access memory exceeds a limit.

48. The method of claim 46 wherein the synchronized access fails because a retry-limit is exceeded.

49. The method of claim 48 further comprising executing an instruction to disable trapping of a retry-limit exception before executing the instruction for accessing memory.