Method and apparatus for propagating error status over an ECC protected channel

• US 7,020,810 B2
• Filed: 07/10/2003
• Issued: 03/28/2006
• Est. Priority Date: 11/29/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Holman, Thomas J.
• Primary Examiner(s): DILDINE JR, R STEPHEN
• Application Number:
  US10/617,541
• Publication Number:
  US 20040107397A1
• Time in Patent Office: 992 Days
• Field of Search: 714/52, 714/701, 714703-704, 714/708, 714/765, 714/753, 714/785
• US Class Current: 714/701
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: H03M 13/01 Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
• CPC Class Codes: H03M 13/03 Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words

Abstract

System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.

Claims

1. A method comprising

determining that data has an uncorrectable error, and

generating an error correction and detection code that comprises the data and a plurality of check bits such that the error correction and detection code indicates the uncorrectable error in the data regardless of a later introduced single bit error in the error correction and detection code.

2. The method of claim 1 wherein generating the error correction and detection code comprises generating the error correction and detection code such that a receiving device can correct single bit errors, detect double bit errors, detect triple bit errors, and detect quadruple bit errors.

3. The method of claim 2 wherein generating the error correction and detection code comprises injecting a triple bit error into the error correction and detection code.

4. The method of claim 3 wherein injecting comprises injecting the triple bit error into a nibble of the error correction and detection code.

5. The method of claim 1 wherein generating the error correction and detection code comprises generating the error correction detection code such that a device, based upon the error correction and detection code, can correct up to a X bit error in the error correction and detection code and can detect up to a Y bit error in the error correction and detection code, where Y is greater than or equal to X+3.

6. The method of claim 5 wherein generating the error correction and detection code comprises injecting a Z bit error into the error correction and detection code, where Z is greater than X+1 and less than Y.

7. A method comprising

generating a code comprising data and a plurality of check bits such that a device, based upon the code, can correct up to a X bit error in the code and can detect up to a Y bit error in the code, where Y is greater than or equal to X+3, and

injecting a Z bit error into the code in response to an uncorrectable error, wherein Z is greater than X+1 and less than Y.

8. The method of claim 7 wherein X equals 1, Y equals 4, and Z equals 3.

9. The method of claim 7 wherein injecting comprises injecting a triple bit error into a nibble of the code.

10. An apparatus comprising

a code generator to generate a code comprising data and a plurality of check bits that a device, based upon the code, can correct up to a X bit error in the code and can detect up to a Y bit error in the code, and

an error injector to inject a Z bit error into the code in response to an uncorrectable error, wherein Z is greater than X+1 and less than Y.

11. The apparatus of claim 10 comprising a controller to receive an error status of the data and to cause the error injector to inject the Z bit error in response to the error status indicating an uncorrectable error.

12. The apparatus of claim 10 wherein X equals 1, Y equals 4, and Z equals 3.

13. The apparatus of claim 10 wherein the error injector injects a triple bit error into a nibble of the code in response to the uncorrectable error.

14. A machine-readable medium comprising a plurality of instructions that in response to being executed result in a device,

determining whether data has an uncorrectable error,

generating a code comprising data and a plurality of check bits such that another device, based upon the code, can correct up to a X bit error in the code and can detect up to a Y bit error in the code, and

injecting a Z bit error into the code in response to determining that the data comprises has the uncorrectable error, wherein Z is greater than X+1 and less than Y.

15. The machine-readable medium of claim 14 wherein executing the plurality of instructions further result in the device

generating the code such that the another device can correct up to a single bit error and can detect up to a quadruple bit error, and

injecting a triple bit error into the code in response to determining that the data has the uncorrectable error.

16. The machine-readable medium of claim 14 wherein executing the plurality of instructions further result in the device injecting a triple bit error into a nibble of the code.

17. A system comprising

a receiving device to receive a code, to correct up to a X bit error of the code, to detect up to a Y bit error of the code, and to detect an uncorrectable error of the code in response to detecting that the code comprises greater than a X bit error, and

a transmitting device to transmit the code such that the code comprises data, a plurality of check bits, and a Z bit error in response to the data having the uncorrectable error, where Z is greater than X+1 and less than Y.

18. The system of claim 17 wherein X equals 1, Y equals 4, and Z equals 3.

19. The system of claim 17 wherein the transmitting device injects a triple bit error into the code prior to transmitting the code.

20. The system of claim 17 wherein the transmitting device injects a triple bit error into a nibble of the code prior to transmitting the code.