Intra-decoder component block messaging

• US 7,020,826 B2
• Filed: 01/23/2002
• Issued: 03/28/2006
• Est. Priority Date: 01/23/2002
• Status: Expired due to Fees

• Current Assignee: Thomson Licensing (Vantiva SA)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Litwin, Louis Robert Jr., Velez, Didier
• Primary Examiner(s): Lamarre, Guy J.
• Application Number:
  US10/055,114
• Publication Number:
  US 20030140301A1
• Time in Patent Office: 1,525 Days
• Field of Search: 714/752, 714/755, 714/758, 714/780, 714/781, 714/782, 714/783, 714/784, 714/785, 714/786, 714/787
• US Class Current: 714/784
• CPC Class Codes: G11B 20/10296 using the Viterbi algorithm
• CPC Class Codes: G11B 20/1803 by redundancy in data representation
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/1555 Pipelined decoder implementations

Abstract

A decoder and decoding method are described, in which a syndrome is calculated from a codeword in a syndrome generator, an error polynomial is generated based upon the syndrome in an error polynomial generator, an error location is determined from the error polynomial in the error location generator, an error magnitude is calculated from the error polynomial in the error magnitude generator and the codeword is corrected by a error corrected codeword generator responsive to location and error magnitude. An intra-decoder block messaging scheme is described in which one or more components generate inactivity messages to signal an ability to process data corresponding to a next codeword. A dual Chien search block implementation is described in which Chien block is used to determine the number of errors corresponding to a specified codeword, separately from error location and magnitude calculations performed by the Chien/Forney block. An enhanced Chien search cell architecture is described which utilizes an additional Galois field adder to synchronize the codeword and error vector, thereby decreasing delay and expense corresponding to an error correcting block implemented with a LIFO register.

Claims

1. In a cyclic linear block code error correcting decoder having at least four blocks, said blocks including a syndrome generating block, an error polynomial block, an error location block, and an error magnitude block, a method for performing data error correction of a codeword, said method comprising the acts of:

calculating a syndrome from said codeword in said syndrome generating block;

generating an error polynomial from said syndrome in said error polynomial block;

determining an error location from said error polynomial in said error location block; and

calculating an error magnitude from said error polynomial in said error magnitude block,

said method characterized in that at least one of said at least four blocks is capable of conveying an inactivity message to other ones of said at least four blocks.

2. The method of claim 1 further comprising the act of:

correcting said codeword responsive to said error location and said error magnitude.

3. The method of claim 1 wherein said inactivity message is a ready-to-receive message.

4. The method of claim 1 wherein said inactivity message is a ready-to-send message.

5. The method of claim 1 wherein said error polynomial block is a Euclid'"'"'s algorithm block.

6. The method of claim 1 wherein said error polynomial block is a Berlekamp-Massey algorithm block.

7. The method of claim 1 wherein said error location block is a Chien search block.

8. The method of claim 1 wherein said error magnitude block is a Forney algorithm block.

9. The method of claim 1 wherein the acts associated with said error location block and said error magnitude block are performed within a combined Chien/Forney block.

10. The method of claim 1 wherein said cyclic linear block code error correcting decoder is a Reed-Solomon decoder.

11. A decoder for performing data error detection within a codeword, said decoder comprising:

means for calculating a syndrome from said codeword;

means for generating an error polynomial from said syndrome;

means for determining an error location from said error polynomial; and

means for calculating an error magnitude from said error polynomial,

said decoder characterized in that an intra-decoder inactivity message conveying capability is incorporated within at least one component selected from a group consisting of said means for calculating said syndrome, said means for generating said error polynomial, said means for determining said error location, and said means for calculating said error magnitude.

12. The decoder of claim 11 further comprising a means for correcting said codeword responsive to receipt of said codeword, said error location, and said error magnitude as inputs.

13. The decoder of claim 11 wherein said decoder is a Reed-Solomon decoder.

14. The decoder of claim 11 wherein said intra-decoder inactivity message is a ready-to-receive message.

15. The decoder of claim 11 wherein said intra-decoder inactivity message is a ready-to-send message.

16. The decoder of claim 11 wherein said means for generating an error polynomial is a Euclid'"'"'s algorithm block.

17. The decoder of claim 11 wherein said means for generating an error location block is a Chien search block.

18. The decoder of claim 11 wherein said means for calculating an error magnitude is a Forney algorithm block.

19. A decoder for performing data error detection within a codeword, said decoder comprising:

a syndrome generator for calculating a syndrome from said codeword;

an error polynomial generator for generating an error polynomial from said syndrome;

an error location generator for determining an error location from said error polynomial; and

an error magnitude generator for calculating an error magnitude from said error polynomial,

said decoder characterized in that an intra-decoder inactivity message convenying capability is incorporated within at least one component selected from a group consisting of said syndrome generator, said error polynomial generator, said error location generator, and said error magnitude generator.

20. The decoder of claim 19 further comprising an error corrected codeword generator for correcting said codeword responsive to receipt of said codeword, said error location, and said error magnitude as inputs.