Design analysis workstation for analyzing integrated circuits

• US 7,020,853 B2
• Filed: 11/21/2003
• Issued: 03/28/2006
• Est. Priority Date: 10/18/2000
• Status: Expired due to Term

• Current Assignee: TechInsights, Inc. (M3, Inc.)
• Original Assignee: Chipworks
• Inventors: Elvidge, Julia, Skoll, David F., Ludlow, Terry
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US10/717,460
• Publication Number:
  US 20040117750A1
• Time in Patent Office: 858 Days
• Field of Search: 716/1, 716/4, 716/5, 716/11, 716/12, 382144-145, 345519-522, 345/964
• US Class Current: 716/111
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2200/24 involving graphical user interfaces [GUIs]
• CPC Class Codes: G06T 2200/32 involving image mosaicing
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06T 7/97 Determining parameters from multiple pictures depth or shape recovery from multiple images G06T7/55; stereo camera calibration G06T7/85

Abstract

A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics. The design analysis workstation provides facilities for performing operations on created annotation objects including grouping, cell definition, signal carrier creation, contact creation, signal propagation, net-list generation, etc. The advantages include annotation of image-mosaics using information derived from a plurality of concurrently displayed mosaic-views to facilitate tracing of interconnected busses and an understanding of interrelations between components.

Claims

1. A system for extracting design and layout information from a plurality of image-mosaics representative of a deconstructed integrated circuit, the system comprising facilities enabling parallel design analysis of the image-mosaics by a plurality of engineer analysts concurrently reverse engineering an integrated circuit (IC), the facilities including:

annotation ownership tracking which assigns an ownership attribute that specifies an engineer analyst associated with the design analysis workstation at a time when the annotation object was created;

unique annotation label generation which generates unique labels to ensure that each annotation label generated is unique across an IC analysis project;

annotation locking which permits a creator of an annotation to prevent other engineer anaysts from changing the annotation object; and

, annotation merging which permits an engineer analyst to load an annotation object owned by another engineer analyst.

2. The system as claimed in claim 1, wherein the system permits the plurality of image-mosaics to be annotated concurrently using a plurality of design analysis workstations.

3. The system as claimed in claim 2, wherein each annotation object created using a design analysis workstation participating in parallel design analysis is provided an ownership attribute by the ownership tracking facility, the ownership attribute specifying an engineer analyst associated with the design analysis workstation at a time when the annotation object was created.

4. The system as claimed in claim 3, wherein the unique annotation label generation facility generates a unique identification string for each annotation objects created using the design analysis workstation.

5. The system as claimed in claim 3, wherein the annotation merging facility merges annotation objects having different ownership attributes for display on one design analysis workstation.

6. The system as claimed in claim 1 wherein the annotation locking facility permits a creator of an annotation object to lock the annotation object to prevent editing of the annotation object by others while the annotation object is locked, so that accidental modification of the annotation object is prevented.

7. The system as claimed in claim 1 wherein the system propagates signal information between components connected by wire and contact annotation objects, each wire and contact annotation object having a property with a signal key and the signal key represents a name of a signal that the associated wire or contact carries, and the facilities prevent propagation of signals by locked annotation objects created by another engineer analyst, but the facilities flag signal conflicts even tough the signals are not propagated.

8. A method of extracting design and layout information from a plurality of image-mosaics representative of a deconstructed integrated circuit the method comprising enabling parallel design analysis of the image-mosaics by a plurality of engineer analysts concurrently reverse engineering an integrated circuit (IC) using multi-user extensions to provide facilities to synchronize work of multiple engineer-analysts working on an IC reverse-engineering project, the facilities enabling parallel design analysis of the image-mosaics by a plurality of engineer analysts concurrently reverse engineering an integrated circuit (IC), including:

annotation ownership tracking which assigns an ownership attribute that specifies an engineer analyst associated with the design analysis workstation at a time when the annotation object was created;

unique annotation label generation which generates unique labels to ensure that each annotation label generated is unique across an IC analysis project;

annotation locking which permits a creator of an annotation to prevent other engineer anaysts from changing the annotation object; and

annotation merging which permits an engineer analyst to load an annotation object owned by another engineer analyst.

9. The method as claimed in claim 8, wherein annotation ownership tracking comprises providing ownership attributes for specifying an engineer analyst associated with a design analysis workstation at a time when the annotation object is created.

10. The method as claimed in claim 9, wherein unique annotation label generation comprises generating a unique identification string for each annotation object.

11. The method as claimed in claim 9, wherein annotation merging comprises merging annotation objects having different ownership attributes for display on one design analysis workstation.

12. The method as claimed in claim 9 wherein annotation locking comprises preventing editing of annotation objects by permitting a creator of an annotation object to lock the annotation object to prevent editing of the annotation object by others while the annotation object is locked.

13. The method as claimed in claim 12 further comprising providing facilities that propagate signal information between components connected by wire and contact annotation objects, each wire and contact annotation object having a property with a signal key that represents a name of a signal that the associated wire or contact carries, and preventing propagation of signals by locked annotation objects created by another engineer analysts, while flagging all signal conflicts even though the signals are not propagated.