×

Digital circuit layout techniques using identification of input equivalence

  • US 7,020,855 B2
  • Filed: 08/16/2002
  • Issued: 03/28/2006
  • Est. Priority Date: 07/17/1998
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of analyzing a digital circuit to identify input equivalences within a circuit, the method comprising:

  • grouping the circuit into one or more regions, each region corresponding to a logic function;

    decomposing the logic function of each of the regions into a directed graph of logic functions;

    identifying equivalent pins by matching pins of the cells in the circuit with points in the directed graph; and

    using the identified pin equivalence information to determine input equivalence, wherein said grouping the circuit into one or more regions comprises decomposing the circuit into fanout-free regions.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×