Breakpoint method for parallel hardware threads in multithreaded processor

• US 7,020,871 B2
• Filed: 12/21/2000
• Issued: 03/28/2006
• Est. Priority Date: 12/21/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Guilford, James D., Hooper, Donald F., Muratori, Richard D., Kornfeld, Serge, Johnson, Desmond R.
• Primary Examiner(s): Zhen, Wei Y.
• Assistant Examiner(s): Steelman, Mary J.
• Application Number:
  US09/747,019
• Publication Number:
  US 20040205747A1
• Time in Patent Office: 1,923 Days
• Field of Search: 717/129, 717/124, 717/127, 717/174, 717/128, 717/130, 703/27, 703/87, 712/32, 712/40, 712/245, 708/231, 700/1, 700/26
• US Class Current: 717/129
• CPC Class Codes: G06F 11/362 Software debugging

Abstract

A method of debugging code that executes in a multithreaded processor having a microengines includes receiving a program instruction and an identification representing a selected one of the microengines from a remote user interface connected to the processor pausing program execution in the threads executing in the selected microengine, inserting a breakpoint after a program instruction in the selected microengine that matches the program instruction received from the remote user interface, resuming program execution in the selected microengine, executing a breakpoint routine if program execution in the selected microengine encounters the breakpoint and resuming program execution in the microengine.

Claims

1. A computer-implemented method comprising:

in parallel hardware threads executing in a processor comprising a plurality of microengines, receiving a source code line to be break pointed in a selected microengine;

determining whether the source code line can be break pointed;

if the source code line can be break pointed, identifying the selected microengine to insert a break point into, which microengine threads to enable breakpoints for, and which microengines to stop if a break point occurs; and

if the source code line cannot be break pointed, signaling an error.

2. The computer-implemented method of claim 1 wherein identifying further comprises generating a break point routine by modifying a template of instructions stored in a debug library.

3. The computer-implemented method of claim 2 wherein identifying further comprises inserting a break point at the source code line and a branch to the source code line.

4. The computer-implemented method of claim 3 further comprising:

executing the parallel hardware threads until the break point is encountered; and

executing the break point routine, the break point routine stopping selected threads and determining which microengine sent an interrupt.

5. The computer-implemented method of claim 4 further comprising displaying program information to a user.

6. The computer-implemented method of claim 5 further comprising resuming execution of the parallel threads in response to a user input.

7. A processor that can execute multiple parallel threads in multiple microengines and that comprises:

a register stack;

a program counter for each executing context;

an arithmetic logic unit coupled to the register stack and a program control store that stores a breakpoint routine that causes the processor to;

receive a source code line to be break pointed in a selected microengine;

determine whether the source code line can be break pointed;

if the source code line can be break pointed, identify the selected microengine to insert a break point into, which microengine threads to enable breakpoints for, and which microengines to stop if a break point occurs; and

if the source code line cannot be break pointed, signal an error.

8. The processor of claim 7 wherein identifying further comprises generating a break point routine by modifying a template of instructions stored in a debug library.

9. The processor of claim 8 wherein identifying further comprises inserting a break point at the source code line and a branch to the source code line.

10. The processor of claim 9 wherein the breakpoint routine further causes the processor to:

execute the parallel threads until the break point is encountered; and

stop selected threads and determine which microengine sent an interrupt.

11. The processor of claim 10 wherein the breakpoint routine further causes the processor to display program information to a user.

12. The processor of claim 11 the breakpoint routine that causes the processor to resume execution of the parallel threads in response to a user input.