Substrate mapping

• US 7,022,533 B2
• Filed: 03/03/2004
• Issued: 04/04/2006
• Est. Priority Date: 08/22/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Gochnour, Derek J.
• Primary Examiner(s): Zarneke, David A.
• Application Number:
  US10/792,230
• Publication Number:
  US 20040171179A1
• Time in Patent Office: 762 Days
• Field of Search: 438/6, 438/14, 438/15, 438/17, 438/107, 438110-112, 438128-130, 438/460, 297/10, 186/64, 235/454, 235/464, 235/494
• US Class Current: 438/15
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49146 with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/53043 including means to divert defective work part
• CPC Class Codes: Y10T 29/53178 Chip component
• CPC Class Codes: Y10T 29/53187 Multiple station assembly apparatus

Abstract

A method for fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.

Claims

1. An assembly method for maintaining integrity of a mounting substrate when attaching a semiconductor die thereto, the mounting substrate having a plurality of die attach sites on a surface thereof comprising:

mapping the plurality of die attach sites on the mounting substrate for determining good die attach sites and defective die attach sites;

storing information for the good die attach sites and the defective die attach sites of the mounting substrate in an electronic file for access therefrom for accessing information of at least one good die attach site on the mounting substrate and for accessing information for at least one defective die attach site on the mounting substrate;

attaching at least one semiconductor die to the mounting substrate using the information by one of attaching a known good die to a good die attach site of the good die attach sites using the information for the good die attach sites; and

attaching a known defective die to a defective die attach site of the defective die attach sites using the information of the defective die attach sites.

2. The method of claim 1, wherein mapping comprises testing at least one die attach site of the plurality of die attach sites on the mounting substrate.

3. The method of claim 1, further comprising providing a designator having substrate identification information on a peripheral portion of the mounting substrate.

4. The method of claim 3, further comprising providing a reading unit for reading the designator to access the information in the electronic file with respect to the mounting substrate corresponding to the substrate identification information.

5. A method for fabricating semiconductor die packages, each package having a mounting substrate having a plurality of die attach sites on at least one surface thereof, the method comprising:

evaluating the plurality of die attach sites on the mounting substrate for determining information regarding good die attach sites; and

for determining defective die attach sites from the information;

attaching at least one semiconductor die to the mounting substrate according to the information by one of attaching a known good die to a good die attach site of the good die attach sites and attaching a known defective die to a defective die attach site of the defective die attach sites using the information regarding the good die attach sites and the defective die attach sites; and

encapsulating the mounting substrate using an encapsulation material for encapsulating at least one known good die and at least one known defective die on the mounting substrate.

6. The method of claim 5, wherein evaluating comprises testing each of the plurality of die attach sites on the mounting substrate.

7. The method of claim 5, further comprising providing the information to an electronic file.

8. The method of claim 7, further comprising providing a designator having substrate identification information on a peripheral portion of the mounting substrate.

9. The method of claim 8, further comprising reading the designator with a reading unit to access the information in the electronic file with respect to the mounting substrate corresponding to the substrate identification information.

10. The method of claim 5, further comprising segregating the at least one semiconductor die attached to the mounting substrate into a semiconductor die package.

11. The method of claim 10, wherein segregating comprises separating from the semiconductor die package at least one semiconductor die package having one of the known good die attached to the good die attach site and the known defective die attached to the defective die attach site according to the information.

12. The method of claim 5, wherein encapsulating comprises transfer molding the mounting substrate.